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FinFET: Digh Hisamoto, Toru Kaga, Yoshifumi Kawamoto, Eiji Takeda Hitachi Central Research Laboratory [57] [58] [59] December 1998: 17 nm: FinFET Digh Hisamoto, Chenming Hu, Tsu-Jae King Liu, Jeffrey Bokor: University of California (Berkeley) [60] [61] 2001 15 nm: FinFET Chenming Hu, Yang-Kyu Choi, Nick Lindert, Tsu-Jae King Liu: University of ...
A double-gate FinFET device. A fin field-effect transistor (FinFET) is a multigate device, a MOSFET (metal–oxide–semiconductor field-effect transistor) built on a substrate where the gate is placed on two, three, or four sides of the channel or wrapped around the channel (gate all around), forming a double or even multi gate structure.
The NEC SX-Aurora TSUBASA processor, introduced in October 2017, [40] used a "16 nm" FinFET process from TSMC and was designed for use with NEC SX supercomputers. [41] [needs update] On July 22, 2018, GlobalFoundries announced their "12 nm" Leading-Performance (12LP) process, based on a licensed 14LP process from Samsung. [42] [needs update]
In semiconductor manufacturing, the 2 nm process is the next MOSFET (metal–oxide–semiconductor field-effect transistor) die shrink after the 3 nm process node.. The term "2 nanometer", or alternatively "20 angstrom" (a term used by Intel), has no relation to any actual physical feature (such as gate length, metal pitch or gate pitch) of the transistors.
FlexFET is a planar, independently double-gated transistor with a damascene metal top gate MOSFET and an implanted JFET bottom gate that are self-aligned in a gate trench. . This device is highly scalable due to its sub-lithographic channel length; non-implanted ultra-shallow source and drain extensions; non-epi raised source and drain regions; and gate-last fl
On January 3, 2010, Intel and Micron Technology announced the first in a family of 25 nm NAND devices. On May 2, 2011, Intel announced its first 22 nm microprocessor, codenamed Ivy Bridge, using a FinFET technology called 3-D tri-gate. [10] IBM's POWER8 processors are produced in a 22 nm SOI process. [11]
Subthreshold leakage in an nFET. Subthreshold conduction or subthreshold leakage or subthreshold drain current is the current between the source and drain of a MOSFET when the transistor is in subthreshold region, or weak-inversion region, that is, for gate-to-source voltages below the threshold voltage.
Stress-induced leakage current (SILC) is an increase in the gate leakage current of a MOSFET, used in semiconductor physics. It occurs due to defects created in the gate oxide during electrical stressing. [1] [2] SILC is perhaps the largest factor inhibiting device miniaturization. Increased leakage is a common failure mode of electronic devices.