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The Universal Verification Methodology (UVM) is a standardized methodology for verifying integrated circuit designs. UVM is derived mainly from OVM ( Open Verification Methodology ) which was, to a large part, based on the eRM (e Reuse Methodology) for the e verification language developed by Verisity Design in 2001.
The e Reuse Methodology was widely accepted by verification engineers and is the most widely used and successful reuse methodology with thousands of successful projects. [citation needed] eRM formed the basis of the URM (Universal Reuse Methodology) developed by Cadence Design Systems for the SystemVerilog verification language.
SystemVerilog, standardized as IEEE 1800, is a hardware description and hardware verification language used to model, design, simulate, test and implement electronic systems.
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The Open Verification Methodology (OVM) is a documented methodology with a supporting building-block library for the verification of semiconductor chip designs. The initial version, OVM 1.0, was released in January, 2008, [ 1 ] and regular updates have expanded its functionality.
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Aspect-oriented programming in e allows verification engineers to structure their testbench in aspects. An object is therefore the sum of all its aspects, which may be distributed over multiple files. The following sections illustrate basic aspect-oriented mechanisms in e.