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  2. Memory controller - Wikipedia

    en.wikipedia.org/wiki/Memory_controller

    A memory controller, also known as memory chip controller (MCC) or a memory controller unit (MCU), is a digital circuit that manages the flow of data going to and from a computer's main memory. [ 1 ] [ 2 ] When a memory controller is integrated into another chip, such as an integral part of a microprocessor , it is usually called an integrated ...

  3. List of PowerPC processors - Wikipedia

    en.wikipedia.org/wiki/List_of_PowerPC_processors

    To keep costs low on high-volume competitive products, the CPU core is usually bundled into a system-on-chip (SOC) integrated circuit. SOCs contain the processor core, cache and the processor's local data on-chip, along with clocking, timers, memory (SDRAM), peripheral (network, serial I/O), and bus (PCI, PCI-X, ROM/Flash bus, I2C) controllers.

  4. Northbridge (computing) - Wikipedia

    en.wikipedia.org/wiki/Northbridge_(computing)

    Intel's Sandy Bridge processors feature full integration of northbridge functions onto the CPU chip, along with processor cores, memory controller, high speed PCI Express interface and integrated graphics processing unit (GPU). This was a further evolution of the Westmere architecture, which also featured a CPU and GPU in the same package. [11]

  5. Platform Controller Hub - Wikipedia

    en.wikipedia.org/wiki/Platform_Controller_Hub

    Block diagram of the Platform Controller Hub–based chipset architecture, including an Integrated Memory Controller (IMC) in the CPU An Intel DH82H81 PCH with its die exposed. The Platform Controller Hub (PCH) is a family of Intel's single-chip chipsets, first introduced in 2009.

  6. Compute Express Link - Wikipedia

    en.wikipedia.org/wiki/Compute_Express_Link

    Coherence mode can be set individually for each 4 KB page, stored in a translation table in local memory of Type 2 devices. Unlike other CPU-to-CPU memory coherency protocols, this arrangement only requires the host CPU memory controller to implement the cache agent; such asymmetric approach reduces implementation complexity and reduces latency.

  7. Southbridge (computing) - Wikipedia

    en.wikipedia.org/wiki/Southbridge_(computing)

    At Intel, the authors of the PCI specification viewed the PCI local bus as being at the very centre of the PC platform architecture (i.e., at the Equator). The northbridge extends to the north of the PCI bus backbone in support of CPU, memory/cache, and other performance-critical capabilities. Likewise the southbridge extends to the south of ...