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  2. Executive dysfunction - Wikipedia

    en.wikipedia.org/wiki/Executive_dysfunction

    The procedure of the CDT begins with the instruction to the participant to draw a clock reading a specific time (generally 11:10). After the task is complete, the test administrator draws a clock with the hands set at the same specific time. Then the patient is asked to copy the image. [37]

  3. List of performance analysis tools - Wikipedia

    en.wikipedia.org/wiki/List_of_performance...

    Arm MAP, a performance profiler supporting Linux platforms.; AppDynamics, an application performance management solution [buzzword] for C/C++ applications via SDK.; AQtime Pro, a performance profiler and memory allocation debugger that can be integrated into Microsoft Visual Studio, and Embarcadero RAD Studio, or can run as a stand-alone application.

  4. Linux Desktop Testing Project - Wikipedia

    en.wikipedia.org/wiki/Linux_Desktop_Testing_Project

    The Linux Desktop Testing Project (LDTP) is a testing tool that uses computer assistive technology [7] to automate graphical user interface (GUI) testing. [8] The GUI functionality of an application can be tested in Linux , macOS , Windows , Solaris , FreeBSD , and embedded system environments. [ 9 ]

  5. Error detection and correction - Wikipedia

    en.wikipedia.org/wiki/Error_detection_and_correction

    Convolutional codes are processed on a bit-by-bit basis. They are particularly suitable for implementation in hardware, and the Viterbi decoder allows optimal decoding. Block codes are processed on a block-by-block basis. Early examples of block codes are repetition codes, Hamming codes and multidimensional parity-check codes.

  6. Digital delay generator - Wikipedia

    en.wikipedia.org/wiki/Digital_delay_generator

    A digital delay generator (also known as digital-to-time converter) is a piece of electronic test equipment that provides precise delays for triggering, syncing, delaying, and gating events. These generators are used in many experiments, controls, and processes where electronic timing of a single event or multiple events to a standard timing ...

  7. Digital timing diagram - Wikipedia

    en.wikipedia.org/wiki/Digital_timing_diagram

    The timing diagram example on the right describes the Serial Peripheral Interface (SPI) Bus. Most SPI master nodes can set the clock polarity (CPOL) and clock phase (CPHA) with respect to the data. This timing diagram shows the clock for both values of CPOL and the values for the two data lines (MISO & MOSI) for each value of CPHA.

  8. Differential Manchester encoding - Wikipedia

    en.wikipedia.org/wiki/Differential_Manchester...

    Differential Manchester encoding (DM) is a line code in digital frequency modulation in which data and clock signals are combined to form a single two-level self-synchronizing data stream. Each data bit is encoded by a presence or absence of signal level transition in the middle of the bit period, followed by the mandatory level transition at ...

  9. DEC Special Graphics - Wikipedia

    en.wikipedia.org/wiki/DEC_Special_Graphics

    This was used very often to draw boxes on the VT100 video terminal and the many emulators, and used by bulletin board software. The designation escape sequence ESC ( 0 (hexadecimal 1B 28 30) switched the codes for lower-case ASCII letters to draw this set, and the sequence ESC ( B (hexadecimal 1B 28 42) switched back. [2] IBM calls it Code page ...