Ad
related to: vlsi design for testability
Search results
Results From The WOW.Com Content Network
IEEE Std 1149.1 (JTAG) Testability Primer A technical presentation on Design-for-Test centered on JTAG and Boundary Scan VLSI Test Principles and Architectures , by L.T. Wang, C.W. Wu, and X.Q. Wen, Chapter 2, 2006.
Test compression is a technique used to reduce the time and cost of testing integrated circuits.The first ICs were tested with test vectors created by hand. It proved very difficult to get good coverage of potential faults, so Design for testability (DFT) based on scan and automatic test pattern generation (ATPG) were developed to explicitly test each gate and path in a design.
ATPG (acronym for both automatic test pattern generation and automatic test pattern generator) is an electronic design automation method or technology used to find an input (or test) sequence that, when applied to a digital circuit, enables automatic test equipment to distinguish between the correct circuit behavior and the faulty circuit behavior caused by defects.
Very-large-scale integration (VLSI) is the process of creating an integrated circuit (IC) by combining millions or billions of MOS transistors onto a single chip. VLSI began in the 1970s when MOS integrated circuit (metal oxide semiconductor) chips were developed and then widely adopted, enabling complex semiconductor and telecommunications technologies.
Williams was named a fellow of the Institute of Electrical and Electronics Engineers in 1988 “for leadership and contributions to the area of design for testability.” [3] In 1989 Williams shared with Edward B. Eichelberger the 1989 IEEE Computer Society W. Wallace McDowell Award [2] “for developing the level-sensitive scan technique of testing solid-state logic circuits and for leading ...
Iddq testing for CMOS VLSI. Artech House Publishers. ISBN 0-89006-726-0. Rajsuman, Rochit (April 2000). "Iddq testing for CMOS VLSI". Proceedings of the IEEE. 88 (4): 544– 568. doi:10.1109/5.843000. S2CID 2481046. (NB. This is a summary of the basic ideas behind Iddq testing, the history of the technique, and many of its characteristics.)
Design Closure is a part of the digital electronic design automation workflow by which an integrated circuit (i.e. VLSI) design is modified ... Design for Testability
The Mead–Conway VLSI chip design revolution, or Mead and Conway revolution, was a very-large-scale integration design revolution starting in 1978 which resulted in a worldwide restructuring of academic materials in computer science and electrical engineering education, and was paramount for the development of industries based on the application of microelectronics.