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SSE4 (Streaming SIMD Extensions 4) is a SIMD CPU instruction set used in the Intel Core microarchitecture and AMD K10 (K8L).It was announced on September 27, 2006, at the Fall 2006 Intel Developer Forum, with vague details in a white paper; [1] more precise details of 47 instructions became available at the Spring 2007 Intel Developer Forum in Beijing, in the presentation. [2]
AMD added a subset of SSE, 19 of them, called new MMX instructions, [3] and known as several variants and combinations of SSE and MMX, shortly after with the release of the original Athlon in August 1999, see 3DNow! extensions. AMD eventually added full support for SSE instructions, starting with its Athlon XP and Duron (Morgan core) processors.
All models support: MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, F16C, Enhanced Intel SpeedStep Technology (EIST), Intel 64, XD bit (an NX bit implementation), TXT, Intel VT-x, Intel EPT, Intel VT-d, Intel VT-c, Intel x8 SDDC, Hyper-threading (except E5-2403 v2 and E5-2407 v2), Turbo Boost (except E5-2403 v2, E5-2407 v2 and E5-2418L v2), AES-NI, Smart Cache.
Based on Sandy Bridge microarchitecture.; All models support: MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, Enhanced Intel SpeedStep Technology (EIST), Intel 64, XD bit (an NX bit implementation), TXT, Intel VT-x, Intel EPT, Intel VT-d, Intel VT-c, [1] Intel x8 SDDC, [3] Hyper-threading (except E5-1603, E5-1607, E5-2603, E5-2609 and E5-4617), Turbo Boost (except E5-1603, E5-1607, E5-2603 ...
Nehalem processors incorporate SSE4.2 SIMD instructions, adding seven new instructions to the SSE 4.1 set in the Core 2 series. The Nehalem architecture reduces atomic operation latency by 50% in an attempt to eliminate overhead on atomic operations such as the LOCK CMPXCHG compare-and-swap instruction.
GFNI is a standalone instruction set extension and can be enabled separately from AVX or AVX-512. Depending on whether AVX and AVX-512F support is indicated by the CPU, GFNI support enables legacy (SSE), VEX or EVEX-coded instructions operating on 128, 256 or 512-bit vectors.
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AVX-512 Foundation (F) – adds several new instructions and expands most 32-bit and 64-bit floating point SSE-SSE4.1 and AVX/AVX2 instructions with EVEX coding scheme to support the 512-bit registers, operation masks, parameter broadcasting, and embedded rounding and exception control