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  2. NVM Express - Wikipedia

    en.wikipedia.org/wiki/NVM_Express

    NVM Express over Fabrics (NVMe-oF) is the concept of using a transport protocol over a network to connect remote NVMe devices, contrary to regular NVMe where physical NVMe devices are connected to a PCIe bus either directly or over a PCIe switch to a PCIe bus.

  3. 3D XPoint - Wikipedia

    en.wikipedia.org/wiki/3D_XPoint

    Development of 3D XPoint began around 2012. [8] Intel and Micron had developed other non-volatile phase-change memory (PCM) technologies previously; [note 1] Mark Durcan of Micron said 3D XPoint architecture differs from previous offerings of PCM, and uses chalcogenide materials for both selector and storage parts of the memory cell that are faster and more stable than traditional PCM ...

  4. Micron Technology - Wikipedia

    en.wikipedia.org/wiki/Micron_Technology

    Micron and Intel created a joint venture in 2005, based in IM Flash Technologies in Lehi, Utah. [15] The two companies formed another joint venture in 2011, IM Flash Singapore, in Singapore. [16] In 2012 Micron became sole owner of this second joint venture. [17] In 2006 Micron acquired Lexar, an American manufacturer of digital media products. [3]

  5. List of Intel chipsets - Wikipedia

    en.wikipedia.org/wiki/List_of_Intel_chipsets

    It integrated DMA controller, an interrupt controller PIC, serial and parallel ports, I/O Control, NMI, Real Time Clock, Timers and power-management logic for the processor. This chipset contains 226,000 transistors using the one-micron CHMOS IV technology. It was available for US$45 in quantities of 1,000. [8] 82365SL - PC Card Interface ...

  6. JMicron - Wikipedia

    en.wikipedia.org/wiki/JMicron

    In the same announcement, they showcased the JMF810, a PCIe Gen II 2-lane controller, and the JMF811, a PCIe Gen II 4-lane SSD controller. These controllers are designed for speeds of up to 1.5 GB/s in sequential read and 1.2 GB/s in sequential write. Another announcement was the JMS577, which is a USB 3.0 to SATA VI Gb/s bridge controller.

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  8. Flash memory - Wikipedia

    en.wikipedia.org/wiki/Flash_memory

    In 2016, Micron and Intel introduced a technology known as CMOS Under the Array/CMOS Under Array (CUA), Core over Periphery (COP), Periphery Under Cell (PUA), or Xtacking, [60] in which the control circuitry for the flash memory is placed under or above the flash memory cell array. This has allowed for an increase in the number of planes or ...

  9. SCSI - Wikipedia

    en.wikipedia.org/wiki/SCSI

    The SCSI ID of a device in a drive enclosure that has a back plane is set either by jumpers or by the slot in the enclosure the device is installed into, depending on the model of the enclosure. In the latter case, each slot on the enclosure's back plane delivers control signals to the drive to select a unique SCSI ID.