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A Sun UltraSPARC II microprocessor (1997) SPARC (Scalable Processor ARChitecture) is a reduced instruction set computer (RISC) instruction set architecture originally developed by Sun Microsystems. [1] [2] Its design was strongly influenced by the experimental Berkeley RISC system developed in the early 1980s.
Sun SPARCstation 1+ "pizzabox", 25 MHz SPARC processor, early 1990s SPARCstation Voyager. The SPARCstation, SPARCserver and SPARCcenter product lines are a series of SPARC-based computer workstations and servers in desktop, desk side (pedestal) and rack-based form factor configurations, that were developed and sold by Sun Microsystems.
The UltraSPARC is a microprocessor developed by Sun Microsystems and fabricated by Texas Instruments, introduced in mid-1995. It is the first microprocessor from Sun to implement the 64-bit SPARC V9 instruction set architecture (ISA). Marc Tremblay was a co-microarchitect.
The T1 is a new-from-the-ground-up SPARC microprocessor implementation that conforms to the UltraSPARC Architecture 2005 specification [1] and executes the full SPARC V9 instruction set. Sun has produced two previous multicore processors (UltraSPARC IV and IV+), but UltraSPARC T1 was its first microprocessor that is both multicore and ...
In September 2010, Oracle announced a range of SPARC T3 processor based servers. [6] [7] These are branded as the "SPARC T3" series, the "SPARC Enterprise" brand being dropped. The SPARC T3-series servers include the T3-1B, a blade server module that fits into the Sun Blade 6000 system. All other T3 based servers are rack mounted systems ...
The chip is the first Sun/Oracle SPARC chip to use dynamic threading [3] and out-of-order execution. [4] It incorporates one floating point unit and one dedicated cryptographic unit per core. [ 2 ] The cores use the 64-bit SPARC Version 9 architecture running at frequencies between 2.85 GHz and 3.0 GHz, and are built in a 40 nm process with a ...
The SPARCclassic (Sun 4/15) is a workstation introduced by Sun Microsystems in November 1992. It is based on the sun4m architecture, and is enclosed in a lunchbox chassis. It shares the code name Sunergy with the SPARCclassic X, SPARCstation LX , and SPARCstation ZX. [ 1 ]
The processor uses the same SPARC S3 core design as its predecessor, the SPARC T4 processor, but is implemented in a 28 nm process and runs at 3.6 GHz. [5] The S3 core is a dual-issue core that uses dynamic threading and out-of-order execution , [ 6 ] incorporates one floating point unit , one dedicated cryptographic unit per core.