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The program counter (PC), [1] commonly called the instruction pointer (IP) in Intel x86 and Itanium microprocessors, and sometimes called the instruction address register (IAR), [2] [1] the instruction counter, [3] or just part of the instruction sequencer, [4] is a processor register that indicates where a computer is in its program sequence.
The program counter (PC) is a register that holds the memory address of the next instruction to be executed. After each instruction copy to the memory address register (MAR), the PC can either increment the pointer to the next sequential instruction, jump to a specified pointer, or branch conditionally to a specified pointer. [2]
The PC is merely another register akin to an accumulator but specifically reserved for holding the number of the RASP's current register-based instruction. Thus, a RASP possesses two "instruction/program" registers: (i) the IR (finite state machine's Instruction Register), and (ii) a PC (Program Counter) for the program stored in the registers.
The program counter is typically set to a hard coded value when the CPU is first powered on, and will hence execute whatever machine code happens to be at this address. Similarly, the program counter can be set to execute whatever machine code is at some arbitrary address, even if this is not valid machine code. This will typically trigger an ...
r15 is the program counter, and not usable as a general purpose register; r13 is the stack pointer; r8–r13 can be switched out for others (banked) on a processor mode switch. Older versions had 26-bit addressing, [35] and used upper bits of the program counter (r15) for status flags, making that register 32-bit. ARM 32-bit (Thumb) 8: 16
Program Counter (PC) – a pointer to the address of the next instruction to be executed for this process; CPU Registers – register set where process needs to be stored for execution for running state; CPU Scheduling Information – information scheduling CPU time; Memory Management Information – page table, memory limits, segment table;
The PC-relative addressing mode can be used to load a register with a value stored in program memory a short distance away from the current instruction. It can be seen as a special case of the "base plus offset" addressing mode, one that selects the program counter (PC) as the "base register".
These "in-flight" instructions can retire at any time, depending on memory access, hits in cache, stalls in the pipeline and many other factors. This can cause performance counter events to be attributed to the wrong instructions, making precise performance analysis difficult or impossible. AMD introduced methods to mitigate some of these ...