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A superscalar processor usually sustains an execution rate in excess of one instruction per machine cycle. But merely processing multiple instructions concurrently does not make an architecture superscalar, since pipelined, multiprocessor or multi-core architectures also achieve that, but with different methods.
Intel's second generation of 32-bit x86 processors, introduced built-in floating point unit (FPU), 8 KB on-chip L1 cache, and pipelining. Faster per MHz than the 386. Small number of new instructions. P5 original Pentium microprocessors, first x86 processor with super-scalar architecture and branch prediction. P6
Superscalar, out-of-order execution, 6 execution units, SMP support PowerPC 620: 1997 5 Out-of-order execution, SMP support PWRficient PA6T 2007 Superscalar, out-of-order execution, 6 execution units R4000: 1991 8 Scalar StrongARM SA-110: 1996 5 Scalar, in-order SuperH SH2: 5 SuperH SH2A: 2006 5 Superscalar, Harvard architecture SPARC ...
For those processors that have only one pipeline per core, interleaved multithreading is the only possible way, because it can issue at most one instruction per cycle. Simultaneous multithreading (SMT): Issue multiple instructions from multiple threads in one cycle. The processor must be superscalar to do so.
Diagram of the Intel Core 2 microarchitecture. In electronics, computer science and computer engineering, microarchitecture, also called computer organization and sometimes abbreviated as μarch or uarch, is the way a given instruction set architecture (ISA) is implemented in a particular processor. [1]
Very long instruction word (VLIW) refers to instruction set architectures that are designed to exploit instruction-level parallelism (ILP). A VLIW processor allows programs to explicitly specify instructions to execute in parallel, whereas conventional central processing units (CPUs) mostly allow programs to specify instructions to execute in sequence only.
This processor was a single-chip design, ran at a higher clock frequency than the R8000, and had larger 32 KB primary instruction and data caches. It was also superscalar, but its major innovation was out-of-order execution. Even with one memory pipeline and simpler FPU, the vastly improved integer performance, lower price, and higher density ...
Some superscalar processors (MIPS R8000, Alpha 21264, and Alpha 21464 (EV8)) fetch each line of instructions with a pointer to the next line. This next-line predictor handles branch target prediction as well as branch direction prediction.