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In computer architecture, cycles per instruction (aka clock cycles per instruction, clocks per instruction, or CPI) is one aspect of a processor's performance: the average number of clock cycles per instruction for a program or program fragment. [1] It is the multiplicative inverse of instructions per cycle.
The number of instructions per second is an approximate indicator of the likely performance of the processor. The number of instructions executed per clock is not a constant for a given processor; it depends on how the particular software being run interacts with the processor, and indeed the entire machine, particularly the memory hierarchy.
Generally speaking, however, complex instructions inflate the number of clock cycles per instruction because they must be decoded into simpler micro-operations actually performed by the hardware. After converting X86 binary to the micro-operations used internally, the total number of operations is close to what is produced for a comparable RISC ...
Before standard benchmarks were available, average speed rating of computers was based on calculations for a mix of instructions with the results given in kilo instructions per second (kIPS). The most famous was the Gibson Mix , [ 2 ] produced by Jack Clark Gibson of IBM for scientific applications in 1959.
As each instruction took 20 cycles, it had an instruction rate of 5 kHz. The first commercial PC, the Altair 8800 (by MITS), used an Intel 8080 CPU with a clock rate of 2 MHz (2 million cycles per second). The original IBM PC (c. 1981) had a clock rate of 4.77 MHz (4,772,727 cycles
The value can therefore only be accurately determined by instruction set simulation, which is rarely practiced. is the clock frequency in cycles per second. = is the average cycles per instruction (CPI) for this benchmark.
When a next-line predictor points to aligned groups of 2, 4, or 8 instructions, the branch target will usually not be the first instruction fetched, and so the initial instructions fetched are wasted. Assuming for simplicity, a uniform distribution of branch targets, 0.5, 1.5, and 3.5 instructions fetched are discarded, respectively.
Another unit of throughput is instructions per cycle (IPC) and its reciprocal, cycles per instruction (CPI), is another unit of latency. Speedup is dimensionless and defined differently for each type of quantity so that it is a consistent metric.