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The Verilog Procedural Interface (VPI), originally known as PLI 2.0, is an interface primarily intended for the C programming language. It allows behavioral Verilog code to invoke C functions, and C functions to invoke standard Verilog system tasks. The Verilog Procedural Interface is part of the IEEE 1364 Programming Language Interface ...
The designers of Verilog wanted a language with syntax similar to the C programming language, which was already widely used in engineering software development. Like C, Verilog is case-sensitive and has a basic preprocessor (though less sophisticated than that of ANSI C/C++).
Verilog-A was created to standardize the Spectre behavioral language in the face of competition from VHDL (an IEEE standard), which was absorbing analog capability from other languages (e.g. MAST). Open Verilog International (OVI, the body that originally standardized Verilog) agreed to support the standardization, provided that it was part of ...
SystemVerilog DPI (Direct Programming Interface) is an interface which can be used to interface SystemVerilog with foreign languages. These foreign languages can be C, C++, SystemC as well as others. DPIs consist of two layers: a SystemVerilog layer and a foreign language layer. Both the layers are isolated from each other.
SystemVerilog for register-transfer level (RTL) design is an extension of Verilog-2005; all features of that language are available in SystemVerilog. Therefore, Verilog is a subset of SystemVerilog. SystemVerilog for verification uses extensive object-oriented programming techniques and is more closely related to Java than Verilog. These ...
Released under the GNU General Public License, Icarus Verilog is free software, an alternative to proprietary software like Cadence's Verilog-XL. As of release 0.9, Icarus is composed of a Verilog compiler (including a Verilog preprocessor) with support for plug-in backends, and a virtual machine that simulates the design.
The original Verilog simulator, Gateway Design's Verilog-XL was the first (and only, for a time) Verilog simulator to be qualified for ASIC (validation) sign-off. After its acquisition by Cadence Design Systems, Verilog-XL changed very little over the years, retaining an interpreted language engine, and freezing language-support at Verilog-1995.
Verilator is a software programming tool which converts the hardware description language Verilog to a cycle-accurate behavioral model in the programming languages C++ or SystemC. The generated models are cycle-accurate and 2-state; as a consequence, the models typically offer higher performance than the more widely used event-driven simulators ...