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  2. Intel microcode - Wikipedia

    en.wikipedia.org/wiki/Intel_Microcode

    Final determination and validation of whether an update can be applied to a processor is performed during decryption via the processor. [18] Each microcode update is specific to a particular CPU revision, and is designed to be rejected by CPUs with a different stepping level. Microcode updates are encrypted to prevent tampering and to enable ...

  3. Microcode - Wikipedia

    en.wikipedia.org/wiki/Microcode

    This approach provides a relatively straightforward method of ensuring software compatibility between different products within a processor family. Some hardware vendors, notably IBM and Lenovo, use the term microcode interchangeably with firmware. In this context, all code within a device is termed microcode, whether it is microcode or machine ...

  4. Transient execution CPU vulnerability - Wikipedia

    en.wikipedia.org/wiki/Transient_execution_CPU...

    Require changes to the CPU design and thus a new iteration of hardware Microcode: Partial to full: Partial to full: None to large Updates the software that the CPU runs on which requires patches to be released for each affected CPU and integrated into every BIOS or operating system OS/VMM Partial: Partial to full: Small to large

  5. Downfall (security vulnerability) - Wikipedia

    en.wikipedia.org/wiki/Downfall_(security...

    Intel promised microcode updates to resolve the vulnerability. [1] The microcode patches have been shown to significantly reduce the performance of some heavily-vectorized loads. [7] Patches to mitigate the effects of the vulnerability have also been created as part of the forthcoming version 6.5 release of the Linux kernel. [8]

  6. Transactional Synchronization Extensions - Wikipedia

    en.wikipedia.org/wiki/Transactional...

    By default, with the updated microcode, the processor would still indicate support for RTM but would always abort the transaction. System software is able to detect this mode of operation and mask support for TSX/TSX-NI from the CPUID instruction, preventing detection of TSX/TSX-NI by applications. System software may also enable the ...

  7. Ivy Bridge (microarchitecture) - Wikipedia

    en.wikipedia.org/wiki/Ivy_Bridge_(microarchitecture)

    The Ivy Bridge-EP processor line announced in September 2013 has up to 12 cores and 30 MB third level cache, with rumors of Ivy Bridge-EX up to 15 cores and an increased third level cache of up to 37.5 MB, [45] [46] although an early leaked lineup of Ivy Bridge-E included processors with a maximum of 6 cores.

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