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In 2005, ARM provided a summary of the numerous vendors who implement ARM cores in their design. [1] Keil also provides a somewhat newer summary of vendors of ARM based processors. [ 2 ] ARM further provides a chart [ 3 ] displaying an overview of the ARM processor lineup with performance and functionality versus capabilities for the more ...
This is a comparison of ARM instruction set architecture application processor cores designed by Arm Holdings (ARM Cortex-A) and 3rd parties. It does not include ARM Cortex-R, ARM Cortex-M, or legacy ARM cores.
Processor SOCs Other products ARM1 ARM1 ARM Evaluation System second processor for BBC Micro: ARM2 ARM2 Acorn Archimedes, ChessMachine: ARM250 ARM250 Acorn Archimedes ARM3 ARM3 Acorn Archimedes ARM60 ARM60 3DO Interactive Multiplayer, Zarlink GPS receiver ARM610 ARM610 Acorn Risc PC 600, Apple Newton 100 series: ARM700: ARM700
ARM7, ARM Cortex-M, ARM Cortex-A (on Jailhouse hypervisor), Hitachi H8, Altera Nios2, Microchip dsPIC (including dsPIC30, dsPIC33, and PIC24), Microchip PIC32, ST Microelectronics ST10, Infineon C167, Infineon Tricore, Freescale PPC e200 (MPC 56xx) (including PPC e200 z0, z6, z7), Freescale S12XS, EnSilica eSi-RISC, AVR, Lattice Mico32, MSP430 ...
For example, the ARM Cortex-A32 supports only AArch32, [163] the ARM Cortex-A34 supports only AArch64, [164] and the ARM Cortex-A72 supports both AArch64 and AArch32. [165] An ARMv9-A processor must support AArch64 at all Exception levels, and may support AArch32 at EL0.
ARM Cortex-A78: 2020 14 Out-of-order superscalar, register renaming, 4-way pipeline decode, 6 instruction per cycle, branch prediction, L3 cache ARM Cortex-A710: 2021 10 ARM Cortex-X1: 2020 13 5-wide decode out-of-order superscalar, L3 cache ARM Cortex-X2: 2021 10 ARM Cortex-X3: 2022 9 ARM Cortex-X4: 2023 10 AVR32 AP7: 7 AVR32 UC3: 3 Harvard ...