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  2. Pentium FDIV bug - Wikipedia

    en.wikipedia.org/wiki/Pentium_FDIV_bug

    Thomas Nicely, a professor of mathematics at Lynchburg College, had written code to enumerate primes, twin primes, prime triplets, and prime quadruplets.Nicely noticed some inconsistencies in the calculations on June 13, 1994, shortly after adding a Pentium system to his group of computers, but was unable to eliminate other factors (such as programming errors, motherboard chipsets, etc.) until ...

  3. Year 2038 problem - Wikipedia

    en.wikipedia.org/wiki/Year_2038_problem

    The year 2038 problem (also known as Y2038, [1] Y2K38, Y2K38 superbug or the Epochalypse [2] [3]) is a time computing problem that leaves some computer systems unable to represent times after 03:14:07 UTC on 19 January 2038.

  4. Hazard (computer architecture) - Wikipedia

    en.wikipedia.org/wiki/Hazard_(computer_architecture)

    In the domain of central processing unit (CPU) design, hazards are problems with the instruction pipeline in CPU microarchitectures when the next instruction cannot execute in the following clock cycle, [1] and can potentially lead to incorrect computation results. Three common types of hazards are data hazards, structural hazards, and control ...

  5. Unrelated-machines scheduling - Wikipedia

    en.wikipedia.org/wiki/Unrelated-machines_scheduling

    Unrelated-machines scheduling is an optimization problem in computer science and operations research.It is a variant of optimal job scheduling.We need to schedule n jobs J 1, J 2, ..., J n on m different machines, such that a certain objective function is optimized (usually, the makespan should be minimized).

  6. Socket 370 - Wikipedia

    en.wikipedia.org/wiki/Socket_370

    Socket 370, also known as PGA370, is a CPU socket first used by Intel for Pentium III and Celeron processors to first complement and later replace the older Slot 1 CPU interface on personal computers. The "370" refers to the number of pin holes in the socket for CPU pins.

  7. Embarrassingly parallel - Wikipedia

    en.wikipedia.org/wiki/Embarrassingly_parallel

    "Embarrassingly" is used here to refer to parallelization problems which are "embarrassingly easy". [4] The term may imply embarrassment on the part of developers or compilers: "Because so many important problems remain unsolved mainly due to their intrinsic computational complexity, it would be embarrassing not to develop parallel implementations of polynomial homotopy continuation methods."

  8. Multiple instruction, multiple data - Wikipedia

    en.wikipedia.org/wiki/Multiple_instruction...

    Each processor has no direct knowledge about other processor's memory. For data to be shared, it must be passed from one processor to another as a message. Since there is no shared memory, contention is not as great a problem with these machines. It is not economically feasible to connect a large number of processors directly to each other.

  9. Very long instruction word - Wikipedia

    en.wikipedia.org/wiki/Very_long_instruction_word

    Very long instruction word (VLIW) refers to instruction set architectures that are designed to exploit instruction-level parallelism (ILP). A VLIW processor allows programs to explicitly specify instructions to execute in parallel, whereas conventional central processing units (CPUs) mostly allow programs to specify instructions to execute in sequence only.