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The Auxiliary Carry flag is set (to 1) if during an "add" operation there is a carry from the low nibble (lowest four bits) to the high nibble (upper four bits), or a borrow from the high nibble to the low nibble, in the low-order 8-bit portion, during a subtraction. Otherwise, if no such carry or borrow occurs, the flag is cleared or "reset ...
Set to a copy of the most significant bit of an arithmetic result. V Overflow flag. Set in case of two's complement overflow. S Sign flag. Unique to AVR, this is always N⊕V, and shows the true sign of a comparison. H Half-carry flag. This is an internal carry from additions and is used to support BCD arithmetic. T Bit copy.
The carry flag is set according to this addition, and subtract with carry computes a+not(b)+C, while subtract without carry acts as if the carry bit were set. The result is that the carry bit is set if a≥b, and clear if a<b. The System/360, [3] ARM, POWER/PowerPC, 6502, MSP430, COP8, Am29000, i960, and 88000 processors use this convention.
The carry, parity, auxiliary carry (or half carry), zero and sign flags are included in many architectures (many modern (RISC) architectures do not have flags, such as carry, and even if they do use flags, then half carry is rare, since BCD math no longer common, and it even has limited support on long mode on x86-64).
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A full adder can also be constructed from two half adders by connecting and to the input of one half adder, then taking its sum-output as one of the inputs to the second half adder and as its other input, and finally the carry outputs from the two half-adders are connected to an OR gate.
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