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Turbo coding is an iterated soft-decoding scheme that combines two or more relatively simple convolutional codes and an interleaver to produce a block code that can perform to within a fraction of a decibel of the Shannon limit.
Proof. We need to prove that if you add a burst of length to a codeword (i.e. to a polynomial that is divisible by ()), then the result is not going to be a codeword (i.e. the corresponding polynomial is not divisible by ()).
The on-line textbook: Information Theory, Inference, and Learning Algorithms, by David J.C. MacKay, contains chapters on elementary error-correcting codes; on the theoretical limits of error-correction; and on the latest state-of-the-art error-correcting codes, including low-density parity-check codes, turbo codes, and fountain codes.
LDPC codes have no limitations of minimum distance, [34] that indirectly means that LDPC codes may be more efficient on relatively large code rates (e.g. 3/4, 5/6, 7/8) than turbo codes. However, LDPC codes are not the complete replacement: turbo codes are the best solution at the lower code rates (e.g. 1/6, 1/3, 1/2). [35] [36]
Serial concatenated convolutional codes; Shaping codes; Slepian–Wolf coding; Snake-in-the-box; Soft-decision decoder; Soft-in soft-out decoder; Sparse graph code; Srivastava code; Stop-and-wait ARQ; Summation check
The algorithm is named after its inventors: Bahl, Cocke, Jelinek and Raviv. [1] This algorithm is critical to modern iteratively-decoded error-correcting codes, including turbo codes and low-density parity-check codes.
Hardware-wise, this turbo code encoder consists of two identical RSC coders, C 1 and C 2, as depicted in the figure, which are connected to each other using a concatenation scheme, called parallel concatenation: In the figure, M is a memory register. The delay line and interleaver force input bits d k to appear in different sequences.
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