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  2. Framebuffer - Wikipedia

    en.wikipedia.org/wiki/Framebuffer

    A frame buffer may be designed with enough memory to store two frames worth of video data. In a technique known generally as double buffering or more specifically as page flipping, the framebuffer uses half of its memory to display the current frame. While that memory is being displayed, the other half of memory is filled with data for the next ...

  3. Huang's law - Wikipedia

    en.wikipedia.org/wiki/Huang's_law

    Jensen Huang, the chief executive officer of Nvidia and the law's namesake, pictured in 2023. Huang's law is the observation in computer science and engineering that advancements in graphics processing units (GPUs) are growing at a rate much faster than with traditional central processing units (CPUs).

  4. Frame rate - Wikipedia

    en.wikipedia.org/wiki/Frame_rate

    Frame rate, most commonly expressed in frame/s, frames per second or FPS, is typically the frequency (rate) at which consecutive images are captured or displayed. This definition applies to film and video cameras , computer animation , and motion capture systems.

  5. Video random-access memory - Wikipedia

    en.wikipedia.org/wiki/Video_random-access_memory

    Video random-access memory (VRAM) is dedicated computer memory used to store the pixels and other graphics data as a framebuffer to be rendered on a computer monitor. [1] It often uses a different technology than other computer memory, in order to be read quickly for display on a screen.

  6. GDDR5 SDRAM - Wikipedia

    en.wikipedia.org/wiki/GDDR5_SDRAM

    Graphics Double Data Rate 5 Synchronous Dynamic Random-Access Memory (GDDR5 SDRAM) is a type of synchronous graphics random-access memory (SGRAM) with a high bandwidth ("double data rate") interface designed for use in graphics cards, game consoles, and high-performance computing. [1]

  7. Registered memory - Wikipedia

    en.wikipedia.org/wiki/Registered_memory

    A high-capacity DIMM might have numerous memory chips, each of which must receive the memory address, and their combined input capacitance limits the speed at which the memory bus can operate. By redistributing the command and address signals within the R-DIMM, this allows more chips to be connected to the memory bus. [7]