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2006-09-07 23:46 Jamesm76 294×587×0 (11839 bytes) I am the author and I release this to the public domain.; 2006-09-07 23:27 Jamesm76 294×587×0 (11827 bytes) SVG drawing of a CMOS NAND gate replacing the older PNG version I had previously uploaded ("CMOS NAND Layout.png").
A CMOS transistor NAND element. V dd denotes positive voltage.. In CMOS logic, if both of the A and B inputs are high, then both the NMOS transistors (bottom half of the diagram) will conduct, neither of the PMOS transistors (top half) will conduct, and a conductive path will be established between the output and Vss (ground), bringing the output low.
Diagram of the NAND gates in a CMOS type 4011 integrated circuit. NAND gates are basic logic gates, and as such they are recognised in TTL and CMOS ICs. The standard, 4000 series, CMOS IC is the 4011, which includes four independent, two-input, NAND gates. These devices are available from many semiconductor manufacturers.
The following other wikis use this file: Usage on ar.wikipedia.org بوابة اقتران سالبة; Usage on en.wikibooks.org Practical Electronics/IC/4011
The 7400 quad 2-input NAND gate was the first product in the series, introduced by Texas Instruments in a military grade metal flat package (5400W) in October 1964. The pin assignment of this early series differed from the de facto standard set by the later series in DIP packages (in particular, ground was connected to pin 11 and the power ...
quad 2-input NAND gate driver 30 Ω 16 74F3037: 74x3038 4 quad 2-input NAND gate open-collector driver 30 Ω 16 74F3038: 74x3040 2 dual 4-input NAND gate driver 30 Ω 16 74F3040: 74x3125 4 quad FET bus switch, output enable active low (14) SN74CBT3125: 74x3126 4 quad FET bus switch, output enable active high (14) SN74CBT3126: 74FCT3244 2
Schematic of basic two-input DTL NAND gate. R3, R4 and V− shift the positive output voltage of the input DL stage below the ground (to cut off the transistor at low input voltage). Diode–transistor logic (DTL) is a class of digital circuits that is the direct ancestor of transistor–transistor logic.
Shown on the right is a circuit diagram of a NAND gate in CMOS logic. If both of the A and B inputs are high, then both the NMOS transistors (bottom half of the diagram) will conduct, neither of the PMOS transistors (top half) will conduct, and a conductive path will be established between the output and V ss (ground), bringing the output low.