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In field-effect transistors (FETs), depletion mode and enhancement mode are two major transistor types, corresponding to whether the transistor is in an on state or an off state at zero gate–source voltage. Enhancement-mode MOSFETs (metal–oxide–semiconductor FETs) are the common switching elements in most integrated circuits.
In n-channel enhancement-mode devices, a conductive channel does not exist naturally within the transistor. With no V GS, dopant ions added to the body of the FET form a region with no mobile carriers called a depletion region. A positive V GS attracts free-floating electrons within the body towards the gate. But enough electrons must be ...
A depletion-mode device with gate tied to the opposite supply rail is a much better load than an enhancement-mode device, acting somewhere between a resistor and a current source. The first depletion-load NMOS circuits were pioneered and made by the DRAM manufacturer Mostek , which made depletion-mode transistors available for the design of the ...
However, at high frequencies or when switching rapidly, a MOSFET may require significant current to charge and discharge its gate capacitance. In an enhancement mode MOSFET, voltage applied to the gate terminal increases the conductivity of the device. In depletion mode transistors, voltage applied at the gate reduces the conductivity. [1]
The MOSFETs are n-type enhancement mode transistors, arranged in a so-called "pull-down network" (PDN) between the logic gate output and negative supply voltage (typically the ground). A pull up (i.e. a "load" that can be thought of as a resistor, see below) is placed between the positive supply voltage and each logic gate output.
For electronic semiconductor devices, a native transistor (or sometimes natural transistor) is a variety of the MOS field-effect transistor that is intermediate between enhancement and depletion modes. Most common is the n-channel native transistor.
The "V" shape of the MOSFET's gate allows the device to deliver a higher amount of current from the source to the drain of the device. The shape of the depletion region creates a wider channel, allowing more current to flow through it. During operation in blocking mode, the highest electric field occurs at the N + /p + junction.
The depletion region is not symmetrically split between the n and p regions - it will tend towards the lightly doped side. [6] A more complete analysis would take into account that there are still some carriers near the edges of the depletion region. [7] This leads to an additional -2kT/q term in the last set of parentheses above.