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SPARC (Scalable Processor ARChitecture) is a reduced instruction set computer (RISC) instruction set architecture originally developed by Sun Microsystems. [1] [2] Its design was strongly influenced by the experimental Berkeley RISC system developed in the early 1980s.
Visual Instruction Set, or VIS, is a SIMD instruction set extension for SPARC V9 microprocessors developed by Sun Microsystems. There are five versions of VIS: VIS 1, VIS 2, VIS 2+, VIS 3 and VIS 4. [1]
An instruction set architecture (ISA) is an abstract model of a computer, also referred to as computer architecture.A realization of an ISA is called an implementation.An ISA permits multiple implementations that may vary in performance, physical size, and monetary cost (among other things); because the ISA serves as the interface between software and hardware.
The SPARC V9 architecture was designed to have only 32 integer and 32 floating-point number registers. The SPARC V9 instruction encoding limited the number of registers specifiable to 32. To specify the extra registers, HPC-ACE has a "prefix" instruction that would immediately follow one or two SPARC V9 instructions.
The TurboSPARC is a microprocessor that implements the SPARC V8 instruction set architecture (ISA) developed by Fujitsu Microelectronics, Inc. (FMI), the United States subsidiary of the Japanese multinational information technology equipment and services company Fujitsu Limited located in San Jose, California.
The Sun Microsystems UltraSPARC processor is a type of RISC microprocessor.. In electronics and computer science, a reduced instruction set computer (RISC) is a computer architecture designed to simplify the individual instructions given to the computer to accomplish tasks.
OpenSPARC is an open-source hardware project, started in December 2005, for CPUs implementing the SPARC instruction architecture. The initial contribution to the project was Sun Microsystems' register-transfer level (RTL) Verilog code for a full 64-bit, 32-thread microprocessor, the UltraSPARC T1 processor.
The floating-point unit consists of five functional units. One executes floating point adds and subtracts, one multiplies, one divides and square-roots. Two units are for executing SIMD instructions defined by the Visual Instruction Set (VIS). The floating-point register file contains thirty-two 64-bit registers.