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A carry-save adder [1] [2] [nb 1] is a type of digital adder, used to efficiently compute the sum of three or more binary numbers. It differs from other digital adders in that it outputs two (or more) numbers, and the answer of the original summation can be achieved by adding these outputs together.
A conditional sum adder [3] is a recursive structure based on the carry-select adder. In the conditional sum adder, the MUX level chooses between two n/2-bit inputs that are themselves built as conditional-sum adder. The bottom level of the tree consists of pairs of 2-bit adders (1 half adder and 3 full adders) plus 2 single-bit multiplexers.
For Monte Carlo simulations, an LCG must use a modulus greater and preferably much greater than the cube of the number of random samples which are required. This means, for example, that a (good) 32-bit LCG can be used to obtain about a thousand random numbers; a 64-bit LCG is good for about 2 21 random samples (a little over two million), etc ...
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If one draws the data-flow diagram for this pair of operations, the (x 0, x 1) to (y 0, y 1) lines cross and resemble the wings of a butterfly, hence the name (see also the illustration at right). A decimation-in-time radix-2 FFT breaks a length-N DFT into two length-N/2 DFTs followed by a combining stage consisting of many butterfly operations.
That is, after two starting values, each number is the sum of the two preceding numbers. The Fibonacci sequence has been studied extensively and generalized in many ways, for example, by starting with other numbers than 0 and 1, by adding more than two numbers to generate the next number, or by adding objects other than numbers.
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