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Intel Haswell Core i7-4771 CPU, sitting atop its original packaging that contains an OEM fan-cooled heatsink. This generational list of Intel processors attempts to present all of Intel's processors from the 4-bit 4004 (1971) to the present high-end offerings. Concise technical data is given for each product.
As of 2020, the x86 architecture is used in most high end compute-intensive computers, including cloud computing, servers, workstations, and many less powerful computers, including personal computer desktops and laptops.
Intel's second generation of 32-bit x86 processors, introduced built-in floating point unit (FPU), 8 KB on-chip L1 cache, and pipelining. Faster per MHz than the 386. Small number of new instructions. P5 original Pentium microprocessors, first x86 processor with super-scalar architecture and branch prediction. P6
The latest badge promoting the Intel Core branding. The following is a list of Intel Core processors.This includes Intel's original Core (Solo/Duo) mobile series based on the Enhanced Pentium M microarchitecture, as well as its Core 2- (Solo/Duo/Quad/Extreme), Core i3-, Core i5-, Core i7-, Core i9-, Core M- (m3/m5/m7/m9), Core 3-, Core 5-, and Core 7- Core 9-, branded processors.
The Intel Core Duo's inclusion of two highly efficient cores on one chip can provide better performance than a Mobile Pentium 4 core, and with much better power-efficiency. On July 27, 2006, Intel's Core 2 processors were released, which offered x86-64 compatibility and eventually displaced Yonah in production.
The Intel swirl logo was the work of DahlinSmithWhite art director Steve Grigg under the direction of Intel president and CEO Andy Grove. [323] [better source needed] The Intel Inside advertising campaign sought public brand loyalty and awareness of Intel processors in consumer computers. [324]
For backward compatibility, programs are required to detect support for RTM in the CPU before using the new instructions. RTM adds three new instructions: XBEGIN , XEND and XABORT . The XBEGIN and XEND instructions mark the start and the end of a transactional code region; the XABORT instruction explicitly aborts a transaction.
The Intel Core & Core 2 processor lines (2006) that succeeded the Pentium 4 model line didn't utilize hyper-threading. The processors based on the Core microarchitecture did not have hyper-threading because the Core microarchitecture was a descendant of the older P6 microarchitecture.