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A microprocessor is distinct from a microcontroller including a system on a chip. [3] [4] A microprocessor is related but distinct from a digital signal processor, a specialized microprocessor chip, with its architecture optimized for the operational needs of digital signal processing. [5]: 104–107 [6]
Diagram of the Intel Core 2 microarchitecture. In electronics, computer science and computer engineering, microarchitecture, also called computer organization and sometimes abbreviated as μarch or uarch, is the way a given instruction set architecture (ISA) is implemented in a particular processor. [1]
Used in Pentium 4, Pentium D, and some Xeon microprocessors. Very long pipeline. The Prescott was a major architectural revision. Later revisions were the first to feature Intel's x86-64 architecture, enhanced branch prediction and trace cache, and eventually support was added for the NX (No eXecute) bit to implement executable-space protection.
The first documented computer architecture was in the correspondence between Charles Babbage and Ada Lovelace, describing the analytical engine.While building the computer Z1 in 1936, Konrad Zuse described in two patent applications for his future projects that machine instructions could be stored in the same storage used for data, i.e., the stored-program concept.
An instruction set architecture (ISA) is an abstract model of a computer, also referred to as computer architecture.A realization of an ISA is called an implementation.An ISA permits multiple implementations that may vary in performance, physical size, and monetary cost (among other things); because the ISA serves as the interface between software and hardware.
Processor design is a subfield of computer science and computer engineering (fabrication) that deals with creating a processor, a key component of computer hardware.. The design process involves choosing an instruction set and a certain execution paradigm (e.g. VLIW or RISC) and results in a microarchitecture, which might be described in e.g. VHDL or Verilog.
Harvard architecture Bobcat: 2011 Out-of-order execution Bulldozer: 2011 20 Shared multithreaded L2 cache, multithreading, multi-core, around 20 stage long pipeline, integrated memory controller, out-of-order, superscalar, up to 16 cores per chip, up to 16 MB L3 cache, Virtualization, Turbo Core, FlexFPU which uses simultaneous multithreading [2]
AMD Zen+ Family 17h – revised Zen architecture (optimisation and die shrink to 12 nm). AMD Zen 2 Family 17h – second generation Zen architecture based on 7 nm process, first architecture designed around chiplet technology. [3] AMD Zen 3 Family 19h – third generation Zen architecture in the optimised 7 nm process with major core redesigns. [4]