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  2. List of AMD processors - Wikipedia

    en.wikipedia.org/wiki/List_of_AMD_processors

    Llano AMD Fusion (K10 cores + Redwood-class GPU) (launch Q2 2011, this is the first AMD APU) uses Socket FM1 Bulldozer architecture; Bulldozer, Piledriver, Steamroller, Excavator (2011–2017) [ edit ]

  3. List of AMD Ryzen processors - Wikipedia

    en.wikipedia.org/wiki/List_of_AMD_Ryzen_processors

    All the CPUs support 24 PCIe 3.0 lanes. 4 of the lanes are reserved as link to the chipset. No integrated graphics. Fabrication process: TSMC 7FF. Bundled with AMD Wraith Stealth; The AMD 4700S and 4800S desktop processors are part of a "desktop kit" that comes bundled with a motherboard and GDDR6 RAM. The CPU is soldered, and provides 4 PCIe 2 ...

  4. Table of AMD processors - Wikipedia

    en.wikipedia.org/wiki/Table_of_AMD_processors

    AMD K5: SSA/5, 5k86 1 No 75–133 50, 60, 66 FSB 8+16 0 Socket 5 Socket 7: discrete: K6 350, 250 AMD K6: Model 6, Littlefoot 1 No 166–300 50, 60, 66 FSB 32+32 0 Socket 7: discrete: MMX + MMX: 250, 180 AMD K6-2: Chomper, Chomper Extended, mobile 166–550 66, 95, 97, 100 FSB 32+32 0, 128 Super Socket 7: MMX, 3DNow! + 3DNow! 250, 180 K6-3 ...

  5. 3 Top Tech Stocks to Buy Right Now - AOL

    www.aol.com/3-top-tech-stocks-buy-094500773.html

    AMD is the world's second-largest producer of x86 CPUs and discrete GPUs. Over the past decade, it gained ground against Intel in CPUs and kept pace with Nvidia in GPUs by selling its comparable ...

  6. AMD Stock Is the Best Play to Be a Cheap Chip Champ - AOL

    www.aol.com/news/amd-stock-best-play-cheap...

    In a landmark bipartisan act of legislation not long ago, the CHIPS and Science Act became a U.S. law. Chipmaker Advanced Micro Devices (NASDAQ:AMD) is certain to benefit from this law, though the ...

  7. Template:AMD Ryzen 1000 series - Wikipedia

    en.wikipedia.org/wiki/Template:AMD_Ryzen_1000_Series

    Common features of Ryzen 1000 desktop CPUs: Socket: AM4. All the CPUs support DDR4-2666 in dual-channel mode. All the CPUs support 24 PCIe 3.0 lanes. 4 of the lanes are reserved as link to the chipset. No integrated graphics. L1 cache: 96 KB (32 KB data + 64 KB instruction) per core. L2 cache: 512 KB per core.