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  2. OR gate - Wikipedia

    en.wikipedia.org/wiki/OR_gate

    There are many offshoots of the original 7432 OR gate, all having the same pinout but different internal architecture, allowing them to operate in different voltage ranges and/or at higher speeds. In addition to the standard 2-input OR gate, 3- and 4-input OR gates are also available. In the CMOS series, these are: 4075: triple 3-input OR gate

  3. Integrated injection logic - Wikipedia

    en.wikipedia.org/wiki/Integrated_injection_logic

    Integrated injection logic (IIL, I 2 L, or I2L) is a class of digital circuits built with multiple collector bipolar junction transistors (BJT). [1] When introduced it had speed comparable to TTL yet was almost as low power as CMOS , making it ideal for use in VLSI (and larger) integrated circuits .

  4. OR-AND-invert - Wikipedia

    en.wikipedia.org/wiki/OR-AND-invert

    Truth table 2-2 OAI INPUT ... OAI-gates can efficiently be implemented as complex gates. An example of a 3-1 OAI-gate is shown in the figure below. [1] Examples of use

  5. Logic gate - Wikipedia

    en.wikipedia.org/wiki/Logic_gate

    A logic circuit diagram for a 4-bit carry lookahead binary adder design using only the AND, OR, and XOR logic gates.. A logic gate is a device that performs a Boolean function, a logical operation performed on one or more binary inputs that produces a single binary output.

  6. NOR gate - Wikipedia

    en.wikipedia.org/wiki/NOR_gate

    The left diagram above show the construction of a 2-input NOR gate using NMOS logic circuitry. If either of the inputs is high, the corresponding N-channel MOSFET is turned on and the output is pulled low; otherwise the output is pulled high through the pull-up resistor. In the CMOS implementation on the right, the function of the pull-up ...

  7. AND gate - Wikipedia

    en.wikipedia.org/wiki/AND_gate

    The AND gate is a basic digital logic gate that implements the logical conjunction (∧) from mathematical logic – AND gates behave according to their truth table. A HIGH output (1) results only if all the inputs to the AND gate are HIGH (1). If all of the inputs to the AND gate are not HIGH, a LOW (0) is outputted.