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PMOS uses p-channel (+) metal-oxide-semiconductor field effect transistors (MOSFETs) to implement logic gates and other digital circuits. PMOS transistors operate by creating an inversion layer in an n-type transistor body. This inversion layer, called the p-channel, can conduct holes between p-type "source" and "drain" terminals.
In PMOS, the polarities are reversed. The mode can be determined by the sign of the threshold voltage (gate voltage relative to source voltage at the point where an inversion layer just forms in the channel): for an N-type FET, enhancement-mode devices have positive thresholds, and depletion-mode devices have negative thresholds; for a P-type ...
The inversion layer confines the flow of minority carriers, increasing modulation and conductivity, although its electron transport depends on the gate's insulator or quality of oxide if used as an insulator, deposited above the inversion layer. Bardeen's patent as well as the concept of an inversion layer forms the basis of CMOS technology today.
When the transistors are extremely scaled down, it is necessary to make the gate dielectric layer very thin, around 1 nm in state-of-the-art technologies. A phenomenon observed here is the so-called poly depletion, where a depletion layer is formed in the gate polysilicon layer next to the gate dielectric when the transistor is in the inversion ...
In semiconductor physics, the depletion region, also called depletion layer, depletion zone, junction region, space charge region, or space charge layer, is an insulating region within a conductive, doped semiconductor material where the mobile charge carriers have diffused away, or been forced away by an electric field. The only elements left ...
As channel length is reduced, the effects of DIBL in the subthreshold region (weak inversion) show up initially as a simple translation of the subthreshold current vs. gate bias curve with change in drain-voltage, which can be modeled as a simple change in threshold voltage with drain bias. However, at shorter lengths the slope of the current ...
Polysilicon depletion effect is the phenomenon in which unwanted variation of threshold voltage of the MOSFET devices using polysilicon as gate material is observed, leading to unpredicted behavior of the electronic circuit. [1] Because of this variation High-k Dielectric Metal Gates (HKMG) were introduced to solve the issue.
A nanowire MOSFET's current–voltage characteristic (left, using logarithmic y-axis) and a simulation of the electron density (right) forming a conductive inversion channel which connects at the ~0.45 V threshold voltage. Extremely little current flows below this voltage.