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Quad SPI (QSPI; different to but has same abbreviation as Queued-SPI described in § Intelligent SPI controllers) goes beyond dual SPI, adding two more I/O lines (SIO2 and SIO3) and sends 4 data bits per clock cycle. Again, it is requested by special commands, which enable quad mode after the command itself is sent in single mode.
Devices implementing SPI are typically specified with line rates of 700~800 Mbit/s and in some cases up to 1 Gbit/s. The latest version is SPI 4 Phase 2 also known as SPI 4.2 delivers bandwidth of up to 16 Gbit/s for a 16 bit interface. The Interlaken protocol, a close variant of SPI-5 replaced the System Packet Interface in the marketplace.
The 16-bit option became the most popular. At 10 MHz with a bus width of 16 bits it is possible to achieve a data rate of 20 MB/s. Subsequent extensions to the SCSI standard allowed for faster speeds: 20 MHz, 40 MHz, 80 MHz, 160 MHz and finally 320 MHz. At 320 MHz x 16 bits there is a theoretical maximum peak data rate of 640 MB/s.
SIMM modules connect to the computer via an 8-bit- or 32-bit-wide interface. RIMM modules used by RDRAM are 16-bit- or 32-bit-wide. [49] DIMM modules connect to the computer via a 64-bit-wide interface. Some other computer architectures use different modules with a different bus width.
Two SPI controllers. One QSPI (quad SPI) controller, supports 1 / 2 / 4-bit SPI transfers, 2 chip selects. Two I²C controllers. One HSTX (high-speed serial transmit) controller, output-only. This is meant for digital video output. 12 PIO (programmable input–output) state machines. 24 PWM channels.
An example SPI with a master and three slave select lines. Note that all four chips share the SCLK, MISO, and MOSI lines but each slave has its own slave select. Chip select (CS) or slave select (SS) is the name of a control line in digital electronics used to select one (or a set) of integrated circuits (commonly called "chips") out of several connected to the same computer bus, usually ...
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Initially, the SCSI Parallel Interface (SPI) was the only interface using the SCSI protocol. Its standardization started as a single-ended 8-bit bus in 1986, transferring up to 5 MB/s, and evolved into a low-voltage differential 16-bit bus capable of up to 320 MB/s. The last SPI-5 standard from 2003 also defined a 640 MB/s speed which failed to ...