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The multilevel page table may keep a few of the smaller page tables to cover just the top and bottom parts of memory and create new ones only when strictly necessary. Now, each of these smaller page tables are linked together by a master page table, effectively creating a tree data structure. There need not be only two levels, but possibly ...
It is also helpful to use large pages in the host page tables to reduce the number of levels (e.g., in x86-64, using 2 MB pages removes one level in the page table). Since memory is typically allocated to virtual machines at coarse granularity, using large pages for guest-physical translation is an obvious optimization, reducing the depth of ...
For a single-level page table, addresses are broken down into a set of bits to index the page table and remaining bits that pass through to the physical address without modification, indexing a byte within the page. For a two-level page table, addresses are borken down into a set of bits to index the root level of the tree, a set of bits to ...
A system with a smaller page size uses more pages, requiring a page table that occupies more space. For example, if a 2 32 virtual address space is mapped to 4 KiB (2 12 bytes) pages, the number of virtual pages is 2 20 = (2 32 / 2 12). However, if the page size is increased to 32 KiB (2 15 bytes), only 2 17 pages are required. A multi-level ...
The page table, generally stored in main memory, keeps track of where the virtual pages are stored in the physical memory. This method uses two memory accesses (one for the page-table entry, one for the byte) to access a byte. First, the page table is looked up for the frame number.
An access descriptor contains permission bits and a 26-bit object index; the object index is an index into a table of object descriptors, giving an object type, an object length, and a physical address for the object's data, a page table for the object, or the top-level page table for a two-level page table for the object, depending on the ...
In traditional 32-bit protected mode, x86 processors use a two-level page translation scheme, where the control register CR3 points to a single 4 KiB-long page directory, which is divided into 1024 × 4-byte entries that point to 4 KiB-long page tables, similarly consisting of 1024 × 4-byte entries pointing to 4 KiB-long pages.
Load the required data into the available page frame. Update the page table to refer to the new page frame. Return control to the program, transparently retrying the instruction that caused the page fault. When all page frames are in use, the operating system must select a page frame to reuse for the page the program now needs.