Ad
related to: amd processor hierarchy chart
Search results
Results From The WOW.Com Content Network
Architecture Fabrication (nm) Family Release Date Code name Model Group Cores SMT Clock rate () Bus Speed & Type [a] Cache Socket Memory Controller Features L1 L2
The AMD 4700S and 4800S desktop processors are part of a "desktop kit" that comes bundled with a motherboard and GDDR6 RAM. The CPU is soldered, and provides 4 PCIe 2.0 lanes. These are reportedly cut-down variants of the APUs found on the PlayStation 5 and Xbox Series X and S repurposed from defective chip stock. [30] [31] [32]
Llano AMD Fusion (K10 cores + Redwood-class GPU) (launch Q2 2011, this is the first AMD APU) uses Socket FM1 Bulldozer architecture; Bulldozer, Piledriver, Steamroller, Excavator (2011–2017) [ edit ]
AMD Family 11h – combined elements of K8 and K10 designs for Turion X2 Ultra / Puma mobile platform. AMD Fusion Family 12h – based on the 10h/K10 design. Includes CPU cores, GPU and Northbridge in the same chip. Llano was the first design which implemented it. Fusion was later re-branded as the APU.
Common features of Ryzen 7000 desktop CPUs: Socket: AM5. All the CPUs support DDR5-5200 in dual-channel mode. L1 cache: 64 KB (32 KB data + 32 KB instruction) per core. L2 cache: 1 MB per core. All the CPUs support 28 PCIe 5.0 lanes. 4 of the lanes are reserved as link to the chipset.
^ A line of Socket F and Socket AM2 processors launched in 2006 were named Athlon 64 FX, the first being the AMD FX-60. ^ A Line of Phenom FX processors was revealed May 2007 and was branded the "FASN8" platform. ^ Sold with a liquid cooling kit.
AMD Ultrathin Platform introduced on January 5, 2011, as the fourth AMD mobile platform targeting the ultra-portable notebook market. It features the 40 nm AMD Ontario (a 9-watt AMD APU for netbooks and small form factor desktops and devices) and Zacate (an 18-watt TDP APU for ultrathin, mainstream, and value notebooks as well as desktops and ...
AMD K6: 1997 6 Superscalar, branch prediction, speculative execution, out-of-order execution, register renaming [b] AMD K6-III: 1999 Branch prediction, speculative execution, out-of-order execution [1] AMD K7: 1999 Out-of-order execution, branch prediction, Harvard architecture: AMD K8: 2003 64-bit, integrated memory controller, 16 byte ...