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Its two inputs S and R can set the internal state to 1 using the combination S=1 and R=0, and can reset the internal state to 0 using the combination S=0 and R=1. [note 1] The SR latch can be constructed from a pair of cross-coupled NOR or NAND logic gates. The stored bit is present on the output marked Q.
If the truth table for a NAND gate is examined or by applying De Morgan's laws, it can be seen that if any of the inputs are 0, then the output will be 1.To be an OR gate, however, the output must be 1 if any input is 1.
dual 4-input NAND gate Schmitt trigger 14 SN74LS18: 74x19 6 hex inverter gate Schmitt trigger 14 SN74LS19: 74x20 2 dual 4-input NAND gate 14 SN74LS20: 74x21 2 dual 4-input AND gate 14 SN74LS21: 74x22 2 dual 4-input NAND gate open-collector 14 SN74LS22: 74x23 2 dual 4-input NOR gate with strobe, one gate expandable with 74x60 16 SN7423: 74x24 4
"A synchronous SR latch (sometimes clocked SR flip-flop) can be made by adding a second level of NAND gates to the inverted SR latch (or a second level of NOR gates to the direct SR latch)." The description does not match the circuit shown below. There are no NAND gates anywhere. A gated SR latch circuit diagram constructed from NOR gates.
The NAND gate has the property of functional completeness, which it shares with the NOR gate. That is, any other logic function (AND, OR, etc.) can be implemented using only NAND gates. [2] An entire processor can be created using NAND gates alone. In TTL ICs using multiple-emitter transistors, it also requires fewer transistors than a NOR gate.
The first part number in the series, the 7400, is a 14-pin IC containing four two-input NAND gates. Each gate uses two input pins and one output pin, with the remaining two pins being power (+5 V) and ground. This part was made in various through-hole and surface-mount packages, including flat pack and plastic/ceramic dual in-line.
Master-Slave DFF has two images: the complete implementation using logic gates and partial schematic using two D-latches. I feel that this is redundant and propose to remove the partial implementation (image on the left) and to change the central image to reflect the fact that it is composed of two D-latches with a NOT in between.
A simple example of metastability can be found in an SR NOR latch, when both Set and Reset inputs are true (R=1 and S=1) and then both transition to false (R=0 and S=0) at about the same time. Both outputs Q and Q are initially held at 0 by the simultaneous Set and Reset inputs.