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  2. Intel AMT versions - Wikipedia

    en.wikipedia.org/wiki/Intel_AMT_versions

    Intel Active Management Technology (AMT) is hardware-based technology built into PCs with Intel vPro technology.AMT is designed to help sys-admins remotely manage PCs out-of-band when PC power is off, the operating system (OS) is unavailable (hung, crashed, corrupted, missing), software management agents are missing, or hardware (such as a hard disk drive or memory) has failed.

  3. List of Intel Xeon chipsets - Wikipedia

    en.wikipedia.org/wiki/List_of_Intel_Xeon_chipsets

    The chipsets contain a 'memory controller hub' and an 'I/O controller hub', which tend to be called 'north bridge' and 'south bridge' respectively. The memory controller hub connects to the processors, memory, high-speed I/O such as PCI Express, and to the I/O controller hub by a proprietary link.

  4. List of Intel chipsets - Wikipedia

    en.wikipedia.org/wiki/List_of_Intel_chipsets

    This version supports Intel486 DX2 CPU. [20] 82360SL - announced in October 1990. [21] It was a chipset for the mobile 80386SL and 80486SL processors. It integrated DMA controller, an interrupt controller PIC, serial and parallel ports, I/O Control, NMI, Real Time Clock, Timers and power-management logic for the processor. This chipset contains ...

  5. List of Intel CPU microarchitectures - Wikipedia

    en.wikipedia.org/wiki/List_of_Intel_CPU_micro...

    The 8088 version, with an 8-bit bus, was used in the original IBM Personal Computer. 186 included a DMA controller, interrupt controller, timers, and chip select logic. A small number of additional instructions. The 80188 was a version with an 8-bit bus. 286 first x86 processor with protected mode including segmentation based virtual memory ...

  6. Input–output memory management unit - Wikipedia

    en.wikipedia.org/wiki/Input–output_memory...

    In computing, an input–output memory management unit (IOMMU) is a memory management unit (MMU) connecting a direct-memory-access–capable (DMA-capable) I/O bus to the main memory. Like a traditional MMU, which translates CPU -visible virtual addresses to physical addresses , the IOMMU maps device-visible virtual addresses (also called device ...

  7. Platform Controller Hub - Wikipedia

    en.wikipedia.org/wiki/Platform_Controller_Hub

    The Intel Management Engine was also moved to the PCH starting with the Nehalem processors and 5-Series chipsets. AMD's chipsets instead use several PCIe lanes to connect with the CPU while also providing their own PCIe lanes, which are also provided by the processor itself. [3] [4] The chipset also contains the Nonvolatile BIOS memory.