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Before 2007 and post-Kaby Lake, some Intel Pentium and Intel Atom (e.g. N270, N450) processors support hyper-threading. Celeron processors never supported it. Intel processors table
Common features of Ryzen 4000 desktop CPUs: Socket: AM4. All the CPUs support DDR4-3200 in dual-channel mode. L1 cache: 64 KB (32 KB data + 32 KB instruction) per core. L2 cache: 512 KB per core. All the CPUs support 24 PCIe 3.0 lanes. 4 of the lanes are reserved as link to the chipset. No integrated graphics. Fabrication process: TSMC 7FF.
Ryzen 5 (1400, Pro 1500, 1500X, Pro 1600, 1600, 1600X) 4/6 ... List of Intel CPU microarchitectures; Comparison of Intel processors This page was last ...
Intel Atom Oak Trail 2-way simultaneous multithreading, in-order, burst mode, 512 KB L2 cache Intel Atom Bonnell: 2008 SMT Intel Atom Silvermont: 2013 Out-of-order execution Intel Atom Goldmont: 2016 Multi-core, out-of-order execution, 3-wide superscalar pipeline, L2 cache Intel Atom Goldmont Plus: 2017 Multi-core Intel Atom Tremont: 2019
The first generation Zen was launched with the Ryzen 1000 series of CPUs (codenamed Summit Ridge) in February 2017. [14] The first Zen-based preview system was demonstrated at E3 2016, and first substantially detailed at an event hosted a block away from the Intel Developer Forum 2016.
Ryzen uses the "Zen" CPU microarchitecture, a redesign that returned AMD to the high-end CPU market after a decade of near-total absence since 2006. [6] AMD's primary competitor, Intel, had largely dominated this market segment starting from the 2006 release of their Core microarchitecture and the Core 2 Duo. [7]
Zen 2 series CPUs and APUs (released 2019) Matisse Ryzen 3000 series (desktop) Castle Peak Ryzen Threadripper 3000 series (desktop) Renoir Ryzen 4000 APU series with RX Vega (desktop & laptop) Lucienne Ryzen 5000 APU series (laptop) Mendocino Ryzen 7020 APU series (laptop) and Athlon 7020 APU series (laptop) Rome Epyc 7002 series (server)
Common features of Ryzen 7000 desktop CPUs: Socket: AM5. All the CPUs support DDR5-5200 in dual-channel mode. L1 cache: 64 KB (32 KB data + 32 KB instruction) per core. L2 cache: 1 MB per core. All the CPUs support 28 PCIe 5.0 lanes. 4 of the lanes are reserved as link to the chipset.