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The VL-Bus operated at the same clock speed as the i486-bus (basically a local bus) while the PCI bus also usually depended on the i486 clock but sometimes had a divider setting available via the BIOS. This could be set to 1/1 or 1/2, sometimes even 2/3 (for 50 MHz CPU clocks).
20 MHz FSB, 40 MHz clock speed. This version of the 20-MHz Overdrive (ODP) was available for the 16- and 20-MHz Intel486 SX CPU for USD $549. [3] 25 MHz FSB, 50 MHz clock speed. The 25-MHz OverDrive (ODP) version was available for USD $699. [4] 33 MHz FSB, 66 MHz clock speed; 25 MHz FSB, 75 MHz clock speed; 33 MHz FSB, 100 MHz clock speed
The Intel 487 "math coprocessor" for 486SX users is a CPU replacement—a 486DX with a different pinout—and originally cost several hundred dollars more than a 387. As prices on Intel's 486 line fell, Cyrix found it more and more difficult for its 486SLC and DLC CPUs to compete and released a fully pin-compatible version of the 486SX and DX ...
[4]: 1–7 This had a clock speed of 16 MHz. [4]: fig 7-3 In Hubble servicing mission 3A the DF-224 (with co-processor) was replaced by the Advanced Computer using a 25 MHz Intel i486, and much more storage [4]: 1–7 The DF-224 was one of the candidate computers for the Space Shuttle, but was not selected. [5]
A version of IntelDX4 featuring write-back cache was released in October 1994. The original write-through versions of the chip are marked with a laser-embossed “&E,” while the write-back-enabled versions are marked “&EW.” i486 OverDrive editions of IntelDX4 had locked multipliers, and therefore can only run at 3× the external clock speed.
The SL was designed for use in mobile computers. It was produced between November 1992 and June 1993. Clock speeds available were 20, 25 and 33 MHz. The i486SL contained all features of the i486DX. In addition, the System Management Mode (SMM) (the same mode introduced with i386SL) was included with this processor. The system management mode ...
The i486SX was a microprocessor originally released by Intel in 1991. It was a modified Intel i486DX microprocessor with its floating-point unit (FPU) disabled. It was intended as a lower-cost CPU for use in low-end systems—selling for US$258—adapting the SX suffix of the earlier i386SX in order to connote a lower-cost option.
In early processors, the TSC was a cycle counter, incrementing by 1 for each clock cycle (which could cause its rate to vary on processors that could change clock speed at runtime) – in later processors, it increments at a fixed rate that doesn't necessarily match the CPU clock speed. [n] Usually 3 [o] Intel Pentium, AMD K5, Cyrix 6x86MX ...