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In digital circuits, an adder–subtractor is a circuit that is capable of adding or subtracting numbers (in particular, binary). Below is a circuit that adds or subtracts depending on a control signal. It is also possible to construct a circuit that performs both addition and subtraction at the same time. [1]
The gate delay can easily be calculated by inspection of the full adder circuit. Each full adder requires three levels of logic. In a 32-bit ripple-carry adder, there are 32 full adders, so the critical path (worst case) delay is 3 (from input to carry in first adder) + 31 × 2 (for carry propagation in latter adders) = 65 gate delays. [6]
The serial binary subtractor operates the same as the serial binary adder, except the subtracted number is converted to its two's complement before being added. . Alternatively, the number to be subtracted is converted to its ones' complement, by inverting its bits, and the carry flip-flop is initialized to a 1 instead of to 0
The full subtractor is a combinational circuit which is used to perform subtraction of three input bits: the minuend , subtrahend , and borrow in . The full subtractor generates two output bits: the difference D {\displaystyle D} and borrow out B out {\displaystyle B_{\text{out}}} .
quad serial adder/subtractor 20 SN74LS385: 74x386 4 quad 2-input XOR gate: 14 SN74LS386: 74x387 1 1024-bit PROM (256x4) open-collector 16 SN74S387: 74x388 1 4-bit D-type register three-state and standard 16 Am74S388: 74x390 2 dual 4-bit decade counter, asynchronous clear 16 SN74LS390: 74x393 2 dual 4-bit binary counter, asynchronous clear 14 ...
A conditional sum adder [3] is a recursive structure based on the carry-select adder. In the conditional sum adder, the MUX level chooses between two n/2-bit inputs that are themselves built as conditional-sum adder. The bottom level of the tree consists of pairs of 2-bit adders (1 half adder and 3 full adders) plus 2 single-bit multiplexers.
An example of a 4-bit Kogge–Stone adder is shown in the diagram. Each vertical stage produces a "propagate" and a "generate" bit, as shown. The culminating generate bits (the carries) are produced in the last stage (vertically), and these bits are XOR'd with the initial propagate after the input (the red boxes) to produce the sum bits. E.g., the first (least-significant) sum bit is ...
For speed, the "reduce partial product" stages are typically implemented as a carry-save adder composed of compressors and the "compute final product" step is implemented as a fast adder (something faster than ripple-carry). Many fast multipliers use full adders as compressors ("3:2 compressors") implemented in static CMOS.