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The NVM Express (NVMe) standard also supports command queuing, in a form optimized for SSDs. [17] NVMe allows multiple queues for a single controller and device, allowing at the same time much higher depths for each queue, which more closely matches how the underlying SSD hardware works.
The SAS is a new generation serial communication protocol for devices designed to allow for much higher speed data transfers and is compatible with SATA. SAS uses a mechanically identical data and power connector to standard 3.5-inch SATA1/SATA2 HDDs, and many server-oriented SAS RAID controllers are also capable of addressing SATA hard drives.
AHCI is separate from the SATA 3 Gbit/s standard, although it exposes SATA's advanced capabilities (such as hot swapping and native command queuing) such that host systems can utilize them. For modern solid state drives, the interface has been superseded by NVMe. [2] The current version of the specification is 1.3.1.
The SATA RAID portion of the product family was called Intel RSTe and the NVMe* RAID portion was called Intel VROC. However, starting in Q1 2019, with the launch of Intel VROC 6.0, the Intel RSTe name was removed, and all RAID solutions in this product family were branded as Intel VROC.
For example, they may be part of a RAID subsystem in which the RAID controller sees the S.M.A.R.T.-capable drive, but the host computer sees only a logical volume generated by the RAID controller. On the Windows platform, many programs designed to monitor and report S.M.A.R.T. information will function only under an administrator account.
Historically, most SSDs used buses such as SATA, SAS, or Fibre Channel for interfacing with the rest of a computer system. Since SSDs became available in mass markets, SATA has become the most typical way for connecting SSDs in personal computers; however, SATA was designed primarily for interfacing with mechanical hard disk drives (HDDs), and it became increasingly inadequate for SSDs, which ...
The ATA standard is supported by both parallel (IDE, PATA) and serial (SATA) ATA hardware. A drawback of the original ATA TRIM command is that it was defined as a non-queueable command and therefore could not easily be mixed with a normal workload of queued read and write operations. SATA 3.1 introduced a queued TRIM command to remedy this. [70]
While the support for AHCI ensures software-level backward compatibility with legacy SATA devices and legacy operating systems, NVM Express is designed to fully utilize high-speed PCI Express storage devices by leveraging their capability of executing many I/O operations in parallel. [8]