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A double-gate FinFET device. A fin field-effect transistor (FinFET) is a multigate device, a MOSFET (metal–oxide–semiconductor field-effect transistor) built on a substrate where the gate is placed on two, three, or four sides of the channel or wrapped around the channel (gate all around), forming a double or even multi gate structure.
Fujio Masuoka, Hiroshi Takato, Kazumasa Sunouchi, N. Okabe Toshiba [54] [55] [56] December 1989: 200 nm: FinFET: Digh Hisamoto, Toru Kaga, Yoshifumi Kawamoto, Eiji Takeda Hitachi Central Research Laboratory [57] [58] [59] December 1998: 17 nm: FinFET Digh Hisamoto, Chenming Hu, Tsu-Jae King Liu, Jeffrey Bokor: University of California (Berkeley ...
In 2005, Toshiba demonstrated a 15 nm FinFET process, with a 15 nm gate length and 10 nm fin width, using a sidewall spacer process. [18] It had erstwhile been suggested in 2003 that for the 16 nm node, a logic transistor would have a gate length of about 5 nm.
Different FinFET structures, which can be modeled by BSIM-CMG. BSIMCMG106.0.0, [65] officially released on March 1, 2012 by UC Berkeley BSIM Group, is the first standard model for FinFETs. BSIM-CMG is implemented in Verilog-A. Physical surface-potential-based formulations are derived for both intrinsic and extrinsic models with finite body doping.
In April 2019, Samsung Electronics announced they had been offering their "5 nm" process (5LPE) tools to their customers since 2018 Q4. [18] In April 2019, TSMC announced that their "5 nm" process (CLN5FF, N5) had begun risk production, and that full chip design specifications were now available to potential customers.
Julius Edgar Lilienfeld, who proposed the concept of a field-effect transistor in 1925.. The concept of a field-effect transistor (FET) was first patented by the Austro-Hungarian born physicist Julius Edgar Lilienfeld in 1925 [1] and by Oskar Heil in 1934, but they were unable to build a working practical semiconducting device based on the concept.