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  2. SATA Express - Wikipedia

    en.wikipedia.org/wiki/SATA_Express

    SATA Express (sometimes unofficially shortened to SATAe) is a computer bus interface that supports both Serial ATA (SATA) and PCI Express (PCIe) storage devices, initially standardized in the SATA 3.2 specification. [1]

  3. NVM Express - Wikipedia

    en.wikipedia.org/wiki/NVM_Express

    SATA Express allows the use of two PCI Express 2.0 or 3.0 lanes and two SATA 3.0 (6 Gbit/s) ports through the same host-side SATA Express connector (but not both at the same time). SATA Express supports NVMe as the logical device interface for attached PCI Express storage devices.

  4. SATA - Wikipedia

    en.wikipedia.org/wiki/SATA

    A 3.5-inch Serial ATA hard disk drive A 2.5-inch Serial ATA solid-state drive. SATA was announced in 2000 [4] [5] in order to provide several advantages over the earlier PATA interface such as reduced cable size and cost (seven conductors instead of 40 or 80), native hot swapping, faster data transfer through higher signaling rates, and more efficient transfer through an (optional) I/O queuing ...

  5. M.2 - Wikipedia

    en.wikipedia.org/wiki/M.2

    The SATA revision 3.2 specification, in its gold revision as of August 2013, standardizes M.2 as a new format for storage devices and specifies its hardware layout. [2]: 12 [8] Buses exposed through the M.2 connector include PCI Express (PCIe) 3.0 and newer, Serial ATA (SATA) 3.0 and USB 3.0; all these standards are backward compatible.

  6. List of Intel Xeon chipsets - Wikipedia

    en.wikipedia.org/wiki/List_of_Intel_Xeon_chipsets

    4× SATA 1.5/3 gigabaud ports C604: 4× SAS/SATA 1.5/3 gigabaud ports C606: 8× SAS/SATA 1.5/3 gigabaud ports optionally through dedicated PCIe 2.0 ×4 (5 GT/s) interface, 1 additional SMBus C608: 8× SAS/SATA 1.5/3 gigabaud ports optionally through dedicated PCIe 2.0 ×4 (5 GT/s) interface, 2 additional SMBus

  7. List of interface bit rates - Wikipedia

    en.wikipedia.org/wiki/List_of_interface_bit_rates

    For instance, SATA revision 3.0 (6 Gbit/s) controllers on one PCI Express 2.0 (5 Gbit/s) channel will be limited to the 5 Gbit/s rate and have to employ more channels to get around this problem. Early implementations of new protocols very often have this kind of problem.