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Peripheral Component Interconnect (PCI) [3] is a local computer bus for attaching hardware devices in a computer and is part of the PCI Local Bus standard. The PCI bus supports the functions found on a processor bus but in a standardized format that is independent of any given processor 's native bus.
Hot-plugging is a supported feature of CompactPCI. Some of the pins are slightly longer to provide proper grounding when devices are inserted and removed. The backplanes can be designed for 3.3 V VIO or 5 V VIO operation. These are differentiated by having 'Cadmium Yellow' coloured key for 3.3V or 'Brilliant Blue' colour for 5V operation.
One of the major improvements the PCI Local Bus had over other I/O architectures was its configuration mechanism. In addition to the normal memory-mapped and I/O port spaces, each device function on the bus has a configuration space, which is 256 bytes long, addressable by knowing the eight-bit PCI bus, five-bit device, and three-bit function numbers for the device (commonly referred to as the ...
Traditionally, a device has an interrupt line (pin) which it asserts when it wants to signal an interrupt to the host processing environment. This traditional form of interrupt signalling is an out-of-band form of control signalling since it uses a dedicated path to send such control information, separately from the main data path.
A power-on self-test (POST) is a process performed by firmware or software routines immediately after a computer or other digital electronic device is powered on. [ 1 ] POST processes may set the initial state of the device from firmware and detect if any hardware components are non-functional.
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If a device has no PnP Expansion header, it may perform any hook in the routine at +03h, as it is a legacy card. In the initial initialization routine, as the Option ROM points to a PCI data structure (not the same as the configuration space), the option ROM code knows the device and vendor ID is at a fixed offset from RIP.
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