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The stroke is named after Henry Maurice Sheffer, who in 1913 published a paper in the Transactions of the American Mathematical Society [10] providing an axiomatization of Boolean algebras using the stroke, and proved its equivalence to a standard formulation thereof by Huntington employing the familiar operators of propositional logic (AND, OR, NOT).
For example, an axiom with six NAND operations and three variables is equivalent to Boolean algebra: [1] (()) ((())) = where the vertical bar represents the NAND logical operation (also known as the Sheffer stroke).
In Boolean logic, logical NOR, [1] non-disjunction, or joint denial [1] is a truth-functional operator which produces a result that is the negation of logical or.That is, a sentence of the form (p NOR q) is true precisely when neither p nor q is true—i.e. when both p and q are false.
definition: is defined as metalanguage:= means "from now on, is defined to be another name for ." This is a statement in the metalanguage, not the object language. The notation may occasionally be seen in physics, meaning the same as :=.
NAND or Sheffer stroke - true when it is not the case that all inputs are true ("not both") NOR or logical nor - true when none of the inputs are true ("neither") XNOR or logical equality - true when both inputs are the same ("equal") An example of a more complicated function is the majority function (of an odd number of inputs).
The vertical bar is a punctuation mark used in computing and mathematics to denote absolute value, logical OR, and pipe commands.
As shown by Alexander V. Kuznetsov, either of the following connectives – the first one ternary, the second one quinary – is by itself functionally complete: either one can serve the role of a sole sufficient operator for intuitionistic propositional logic, thus forming an analog of the Sheffer stroke from classical propositional logic: [6]
A CMOS transistor NAND element. V dd denotes positive voltage.. In CMOS logic, if both of the A and B inputs are high, then both the NMOS transistors (bottom half of the diagram) will conduct, neither of the PMOS transistors (top half) will conduct, and a conductive path will be established between the output and Vss (ground), bringing the output low.