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A floating-point unit (FPU), numeric processing unit (NPU), [1] colloquially math coprocessor, is a part of a computer system specially designed to carry out operations on floating-point numbers. [2] Typical operations are addition , subtraction , multiplication , division , and square root .
Addition of (1.3.2.3)-minifloats. The graphic demonstrates the addition of even smaller (1.3.2.3)-minifloats with 6 bits. This floating-point system follows the rules of IEEE 754 exactly. NaN as operand produces always NaN results. Inf − Inf and (−Inf) + Inf results in NaN too (green area).
Conversely to floating-point arithmetic, in a logarithmic number system multiplication, division and exponentiation are simple to implement, but addition and subtraction are complex. The ( symmetric ) level-index arithmetic (LI and SLI) of Charles Clenshaw, Frank Olver and Peter Turner is a scheme based on a generalized logarithm representation.
The IEEE Standard for Floating-Point Arithmetic (IEEE 754) is a technical standard for floating-point arithmetic originally established in 1985 by the Institute of Electrical and Electronics Engineers (IEEE). The standard addressed many problems found in the diverse floating-point implementations that made them difficult to use reliably and ...
Saturation arithmetic is a version of arithmetic in which all operations, such as addition and multiplication, are limited to a fixed range between a minimum and maximum value. If the result of an operation is greater than the maximum, it is set (" clamped ") to the maximum; if it is below the minimum, it is clamped to the minimum.
For example, floating-point addition is not associative since the rounding errors introduced can depend on the order of the additions. This means that the result of (+) + is sometimes different from the result of + (+). [121] The most common technical standard used for floating-point arithmetic is called IEEE 754.