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The two n-type transistors on the bottom in parallel set the output Y to low (zero) when either A or B is high; the two p-type transistors in series at the top pull the output to high (one) if both inputs are zero. Because p-type transistors are slower than n-type transistors, a NOR gate is less efficient than a NAND gate in CMOS.
Original file (SVG file, nominally 268 × 153 pixels, file size: 4 KB) This is a file from the Wikimedia Commons . Information from its description page there is shown below.
This OR gate is implemented as an AND gate with both inputs inverted(by using PMOS at the top) as well as the output (inverter at the right) which is functionally correct, but is not commonly used as it requires 2 extra transistors. Date: 12 July 2006: Source: Own work using: Inkscape 0.43: Author: inductiveload: SVG development
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File information Description Venn Diagrams Representing all Intersectional Logic Gates Between Two Inputs. Based on Image:LogicGates.jpg. Source I (ZanderSchubert ) created this work entirely by myself. Date 09:39, 19 September 2009 (UTC) Author ZanderSchubert Permission (Reusing this file) See below.
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