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Front panel of the SDS Sigma 5 computer at the Computer History Museum. The SDS Sigma series is a series of third generation computers [1] [2] [3] that were introduced by Scientific Data Systems of the United States in 1966. [4]
The Xerox Sigma 9 was a major re-design with instruction lookahead and other advanced features, while the Sigma 8 and Sigma 9 mod 3 were low-end machines offered as a migration path for the Sigma 5. The French company CII , as a licensee of SDS, sold about 60 Sigma 7 machines in Europe, and developed an upgrade with virtual memory and dual ...
SDS BASIC, also known as CP-V BASIC, Batch BASIC or Sigma BASIC depending on the version, is a BASIC programming language compiler for Scientific Data Systems's (SDS) Sigma series mainframe computers, originally released in 1967.
The Universal Time-Sharing System (UTS) is a discontinued operating system for the XDS Sigma series of computers, succeeding Batch Processing Monitor (BPM)/Batch Time-Sharing Monitor (BTM). UTS was announced in 1966, but because of delays did not actually ship until 1971.
There were 3 models built, the Sigma 9, the Sigma 9 Model 2 and the Sigma 9 Model 3. The original was the most powerful and was universally applicable to all data processing applications at the time. The Model 2 was able to process in multi-programmed batch, remote batch, conversational time-sharing, real-time, and transaction processing modes.
An 18-bit word length (for data, not addresses) was optionally available. A basic machine cycle took 1.8 microseconds, and the core memory read time was 700 nanoseconds. The computers use two's complement arithmetic and had four main registers - accumulator A, accumulator extension B, an index register X and a program counter register ...
For example, a simple comparator has 2 levels and so is 1 bit quantizer; a 3-level quantizer is called a 1.5 bit quantizer; a 4-level quantizer is a 2-bit quantizer; a 5-level quantizer is called a 2.5-bit quantizer. [12] Higher bit quantizers inherently produce less quantization noise.
In addition, new smaller core memory was used that improved the cycle time from the original's 1,200 ns to 800 ns, offering a further 1 / 3 improvement. Performance could be further improved by replacing the core with read-only memory ; lacking core's read–write cycle, this could be accessed in 300 ns for a dramatic performance boost.