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Column address strobe latency, also called CAS latency or CL, is the delay in clock cycles between the READ command and the moment data is available. [ 1 ] [ 2 ] In asynchronous DRAM , the interval is specified in nanoseconds (absolute time). [ 3 ]
With this 1 ns clock, a CAS latency of 7 gives an absolute CAS latency of 7 ns. Faster DDR3-2666 memory (with a 1333 MHz clock, or 0.75 ns exactly; the 1333 is rounded) may have a larger CAS latency of 9, but at a clock frequency of 1333 MHz the amount of time to wait 9 clock cycles is only 6.75 ns.
At higher clock rates, the useful CAS latency in clock cycles naturally increases. 10–15 ns is 2–3 cycles (CL2–3) of the 200 MHz clock of DDR-400 SDRAM, CL4-6 for DDR2-800, and CL8-12 for DDR3-1600. Slower clock cycles will naturally allow lower numbers of CAS latency cycles.
In FPM DRAM, the column address can be supplied while CAS is still deasserted, and the main column access time (t AA) begins as soon as the address is stable. The CAS signal is only needed to enable the output (the data out pins were held at high-Z while CAS was deasserted), so time from CAS assertion to data valid (t CAC) is greatly reduced. [63]
Notable improvements in DDR4 include increased data transfer rates and enhanced efficiency. Early DDR4 samples, such as those from Samsung in January 2011, showed a CAS latency of 13 clock cycles, comparable to the DDR2 to DDR3 transition.
Memory latency is the time (the latency) between initiating a request for a byte or word in memory until it is retrieved by a processor. If the data are not in the processor's cache , it takes longer to obtain them, as the processor will have to communicate with the external memory cells.
The highest-rated DDR2 modules in 2009 operate at 533 MHz (1066 MT/s), compared to the highest-rated DDR modules operating at 200 MHz (400 MT/s). At the same time, the CAS latency of 11.2 ns = 6 / (bus clock rate) for the best PC2-8500 modules is comparable to that of 10 ns = 4 / (bus clock rate) for the best PC-3200 modules.
CAS latency (CL), clock cycle time (t CK), row cycle time (t RC), refresh row cycle time (t RFC), row active time (t RAS). Buffering Registered (or buffered) vs unbuffered. Packaging Typically DIMM or SO-DIMM. Power consumption