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Socket AM5 (LGA 1718) is a zero insertion force flip-chip land grid array (LGA) [1] CPU socket designed by AMD that is used for AMD Ryzen microprocessors starting with the Zen 4 microarchitecture. [ 2 ] [ 3 ] AM5 was launched in September 2022 and is the successor to AM4 .
AM3+ socket support AMD 990X chipset RD980 2600 (HT 3.0) x8 + x8 x8 + x8 14 Two PCIe 2.0 x16, IOMMU. AM3+ socket support AMD 990FX chipset RD990 x16 + x16 or x8 quad x16 + x16 or x16 + x8 + x8 or x8 quad 19.6 Four PCIe 2.0 x16, IOMMU. AM3+ socket support Model Code name Released CPU support Fab (nm) HT (MHz) AMD-V (Hardware Virtualization) IGP ...
Socket 939: Troy 200 Socket 940: Athens 800 Denmark 100 2 1600–3200 1000 HT Socket 939: AMD64, NX Bit: Italy 200 1600–3200 Socket 940: AMD64, NX Bit, ccNUMA: Egypt 800 1600–3200 Santa Ana 1200 1800–3200 Socket AM2: DDR2: AMD64, NX Bit: Santa Rosa 2200 1800–3200 Socket F: 8200 2000–3000 130 Athlon 64 FX: Sledgehammer FX-51, FX-53 1 ...
AGESA releases for socket AM5; Name Microarchitecture Version Release Notes Release Date ComboAM5PI Zen 5 Zen 4 1.2.0.3 Improve system performance December 2024 1.2.0.2 Reduced inter-core latency September 2024 1.2.0.1 Fixed security vulnerabilities (AMD-SB-7014) August 2024 1.2.0.0a Performance, bugfixes June 2024 FireRangePi 1.1.7.0 Patch A
PCIe lanes [d] Gen 4 None ×8 ×12 ×8 ×12 Gen 3 Up to ×8 Up to ×4 Up to ×8 Up to ×4 Up to ×8 USB support USB 2.0: 6 12 6 12 USB 3.2 Gen 1x1 (5 Gb/s) 2 None USB 3.2 Gen 2x1
Socket: AM5. All the CPUs support DDR5 -5200 RAM in dual-channel mode in 2x1R and 2x2R configuration, but only DDR5-3600 for 4x1R and 4x2R. L1 cache : 64 KB (32 KB data + 32 KB instruction) per core.
Llano AMD Fusion (K10 cores + Redwood-class GPU) (launch Q2 2011, this is the first AMD APU) uses Socket FM1 Bulldozer architecture; Bulldozer, Piledriver, Steamroller, Excavator (2011–2017) [ edit ]
Printable version; In other projects ... Socket 754; Socket 939; Socket A ... Socket AM2+ Socket AM3; Socket AM3+ Socket AM4; Socket AM5; Socket FM1; Socket FM2 ...