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This is a comparison of ARM instruction set architecture application processor cores designed by Arm Holdings (ARM Cortex-A) and 3rd parties. It does not include ARM Cortex-R, ARM Cortex-M, or legacy ARM cores.
This is a list of central processing units based on the ARM family of instruction sets designed by ARM Ltd. and third parties, sorted by version of the ARM instruction set, release and name. In 2005, ARM provided a summary of the numerous vendors who implement ARM cores in their design. [ 1 ]
ARM Cortex-A15 MPCore: 2010 15 Multi-core (up to 16), out-of-order, speculative issue, 3-way superscalar ARM Cortex-A53: 2012 Partial dual-issue, in-order ARM Cortex-A55: 2017 8 in-order, speculative execution ARM Cortex-A57: 2012 Deeply out-of-order, wide multi-issue, 3-way superscalar ARM Cortex-A72: 2015 ARM Cortex-A73: 2016 Out-of-order ...
This is a list of products using processors (i.e. central processing units) based on the ARM architecture family, sorted by generation release and name. List of products [ edit ]
In 2005, about 98% of all mobile phones sold used at least one ARM processor. [52] In 2010, producers of chips based on ARM architectures reported shipments of 6.1 billion ARM-based processors, representing 95% of smartphones, 35% of digital televisions and set-top boxes, and 10% of mobile computers.
The ARM Neoverse is a group of 64-bit ARM processor cores licensed by Arm Holdings. The cores are intended for datacenter, edge computing, and high-performance computing use. The group consists of ARM Neoverse V-Series, ARM Neoverse N-Series, and ARM Neoverse E-Series. [1] [2]
This is a list of MediaTek processors for use in smartphones, tablets, smartwatches, IoT, smart TVs and smartbooks. Smartphone processors from ARMv5 to ARMv8 (2003–2019) [ edit ]
The ARM Cortex-A57 is a central processing unit implementing the ARMv8-A 64-bit instruction set designed by ARM Holdings. The Cortex-A57 is an out-of-order superscalar pipeline. [ 1 ] It is available as SIP core to licensees, and its design makes it suitable for integration with other SIP cores (e.g. GPU , display controller , DSP , image ...