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An and-inverter graph (AIG) is a directed, acyclic graph that represents a structural implementation of the logical functionality of a circuit or network.An AIG consists of two-input nodes representing logical conjunction, terminal nodes labeled with variable names, and edges optionally containing markers indicating logical negation.
A CMOS transistor NAND element. V dd denotes positive voltage.. In CMOS logic, if both of the A and B inputs are high, then both the NMOS transistors (bottom half of the diagram) will conduct, neither of the PMOS transistors (top half) will conduct, and a conductive path will be established between the output and Vss (ground), bringing the output low.
2006-09-07 23:46 Jamesm76 294×587×0 (11839 bytes) I am the author and I release this to the public domain.; 2006-09-07 23:27 Jamesm76 294×587×0 (11827 bytes) SVG drawing of a CMOS NAND gate replacing the older PNG version I had previously uploaded ("CMOS NAND Layout.png").
Diagram of the NAND gates in a CMOS type 4011 integrated circuit. NAND gates are basic logic gates, and as such they are recognised in TTL and CMOS ICs. The standard, 4000 series, CMOS IC is the 4011, which includes four independent, two-input, NAND gates. These devices are available from many semiconductor manufacturers.
123D Circuits In-browser circuit design and PCB layout tools. Created by Autodesk, it is free to use, zero-install and web based. There's a limited library of components to use. There are 3 drawing modes: schematics, PCB and breadboard diagram. The PCB editor does not do automatic routing.
Crossover_nand.pdf (795 × 383 pixels, file size: 22 KB, MIME type: application/pdf) This is a file from the Wikimedia Commons . Information from its description page there is shown below.
quad 2-input NAND gate: 14 SN74LS00: 74x01 4 quad 2-input NAND gate; different pinout for 74H01 open-collector: 14 SN74LS01: 74x02 4 quad 2-input NOR gate: 14 SN74LS02: 74x03 4 quad 2-input NAND gate open-collector 14 SN74LS03: 74x04 6 hex inverter gate: 14 SN74LS04: 74x05 6 hex inverter gate open-collector 14 SN74LS05: 74x06 6 hex inverter gate
Schematic of basic two-input DTL NAND gate. R3, R4 and V− shift the positive output voltage of the input DL stage below the ground (to cut off the transistor at low input voltage). Diode–transistor logic ( DTL ) is a class of digital circuits that is the direct ancestor of transistor–transistor logic .