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x86 virtualization is the use of hardware-assisted virtualization capabilities on an x86/x86-64 CPU.. In the late 1990s x86 virtualization was achieved by complex software techniques, necessary to compensate for the processor's lack of hardware-assisted virtualization capabilities while attaining reasonable performance.
Instruction set extensions that have been added to the x86 instruction set in order to support hardware virtualization.These extensions provide instructions for entering and leaving a virtualized execution context and for loading virtual-machine control structures (VMCSs), which hold the state of the guest and host, along with fields which control processor behavior within the virtual machine.
x86, x86-64 (with Intel VT-x or AMD-V, and VirtualBox 2 or later) Windows, Linux, macOS, Solaris, FreeBSD, eComStation DOS, Linux, macOS, [ 8 ] FreeBSD, Haiku , OS/2, Solaris, Syllable, Windows, and OpenBSD (with Intel VT-x or AMD-V, due to otherwise tolerated incompatibilities in the emulated memory management).
In 2005 and 2006, Intel and AMD (working independently) created new processor extensions to the x86 architecture called Intel VT-x and AMD-V, respectively. On the Itanium architecture, hardware-assisted virtualization is known as VT-i. The first generation of x86 processors to support these extensions were released in late 2005 early 2006:
The current Intel vPro emblem. Intel vPro technology is an umbrella marketing term used by Intel for a large collection of computer hardware technologies, including VT-x, VT-d, Trusted Execution Technology (TXT), and Intel Active Management Technology (AMT). [1]
All models support: MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, AVX-512, FMA3, MPX, Enhanced Intel SpeedStep Technology (EIST), Intel 64, XD bit (an NX bit implementation), Intel VT-x, Intel VT-d, Turbo Boost (excluding W-2102 and W-2104), Hyper-threading (excluding W-2102 and W-2104), AES-NI, Intel TSX-NI, Smart Cache. PCI Express ...
Mode Based Execution Control (MBEC) is an extension to x86 SLAT implementations first available in Intel Kaby Lake and AMD Zen+ CPUs (known on the latter as Guest Mode Execute Trap or GMET). [10] The extension extends the execute bit in the extended page table (guest page table) into 2 bits - one for user execute, and one for supervisor execute.
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