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SPARC (Scalable Processor ARChitecture) is a reduced instruction set computer (RISC) instruction set architecture originally developed by Sun Microsystems. [1] [2] Its design was strongly influenced by the experimental Berkeley RISC system developed in the early 1980s.
Visual Instruction Set, or VIS, is a SIMD instruction set extension for SPARC V9 microprocessors developed by Sun Microsystems. There are five versions of VIS: VIS 1, VIS 2, VIS 2+, VIS 3 and VIS 4. There are five versions of VIS: VIS 1, VIS 2, VIS 2+, VIS 3 and VIS 4.
An instruction set architecture (ISA) is an abstract model of a computer, also referred to as computer architecture.A realization of an ISA is called an implementation.An ISA permits multiple implementations that may vary in performance, physical size, and monetary cost (among other things); because the ISA serves as the interface between software and hardware.
A common misunderstanding of the phrase "reduced instruction set computer" is that instructions are simply eliminated, resulting in a smaller set of instructions. [35] In fact, over the years, RISC instruction sets have grown in size, and today many of them have a larger set of instructions than many CISC CPUs.
OpenSPARC is an open-source hardware project, started in December 2005, for CPUs implementing the SPARC instruction architecture. The initial contribution to the project was Sun Microsystems' register-transfer level (RTL) Verilog code for a full 64-bit, 32-thread microprocessor, the UltraSPARC T1 processor.
The SPARC V9 architecture was designed to have only 32 integer and 32 floating-point number registers. The SPARC V9 instruction encoding limited the number of registers specifiable to 32. To specify the extra registers, HPC-ACE has a "prefix" instruction that would immediately follow one or two SPARC V9 instructions.
The floating-point unit consists of five functional units. One executes floating point adds and subtracts, one multiplies, one divides and square-roots. Two units are for executing SIMD instructions defined by the Visual Instruction Set (VIS). The floating-point register file contains thirty-two 64-bit registers.
SPARC V8 ESA: VHDL LEON3/4: Aeroflex Gaisler Yes AMBA2 SPARC V8 Aeroflex Gaisler: VHDL OpenPiton: Princeton Parallel Group Yes Manycore SPARC V9: OpenPiton: Verilog OpenSPARC T1: Sun: Yes 64-bit OpenSPARC.net: Verilog Tacus/PIPE5 TemLib Yes Pipelined bus SPARC V8 TEMLIB: VHDL based on the x86 instruction set architecture: CPU86 HT-Lab Yes 8088 ...