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OpenRISC is a project to develop a series of open-source hardware based central processing units (CPUs) on established reduced instruction set computer (RISC) principles. It includes an instruction set architecture (ISA) using an open-source license. It is the original flagship project of the OpenCores community.
Auctor [8] / ACC Micro [9] - Maple SoC (Cx486DX4 [10] core at 100 to 133 MHz) Advantech - EVA-X4150 and EVA-X4300 (SoCs with 486SX-compatible processors at 150 MHz and 300 MHz, respectively) [11] Innovasic - pin-compatible 80186/80188 clones [12] Vadem - VG230 and VG330 (SoCs with NEC V30 CPU cores, manufacturing continued by Amphus) [13]
RISC-V [b] (pronounced "risk-five" [2]: 1 ) is an open standard instruction set architecture (ISA) based on established reduced instruction set computer (RISC) principles. . The project began in 2010 at the University of California, Berkeley, transferred to the RISC-V Foundation in 2015, and on to RISC-V International, a Swiss non-profit entity, in November 20
OpenSPARC, a series of open-source microprocessors based on the UltraSPARC T1 and UltraSPARC T2 multicore processor designs; Parallax P8X32A Propeller is a multicore microcontroller with an emphasis on general-purpose use; ZPU, a small, portable CPU core with a GCC toolchain. It is designed to be compiled targeting FPGA [4]
Open source, multithreading, multi-core, 4 threads per core, scalar, in-order, integrated memory controller, 1 FPU UltraSPARC T2: 2007 8 Open source, multithreading, multi-core, 8 threads per core SPARC T3: 2010 8 Multithreading, multi-core, 8 threads per core, SMP, 16 cores per chip, 2 MB L3 cache, in-order, hardware random number generator
The relevant term is of the porting target is computer architecture; it comprises the instruction set(s) and the microarchitecture(s) of the processor(s), at least of the CPU. The target also comprises the "system design" of the entire system, be it a supercomputer , a desktop computer or some SoC , e.g. in case some unique bus is being used.
The OpenRISC 1200 (OR1200) is an implementation of the open source OpenRISC 1000 RISC architecture. [1] [better source needed] A synthesizable CPU core, it was for many years maintained by developers at OpenCores.org, although, since 2015, that activity has now been taken over by the Free and Open Source Silicon Foundation at the librecores.org ...
The Amber processor core is an ARM architecture-compatible 32-bit reduced instruction set computing (RISC) processor. It is open source, hosted on the OpenCores website, and is part of a movement to develop a library of open source hardware projects. [1]